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@@ -102,6 +102,7 @@ struct pl08x_driver_data;
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* missing
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*/
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struct vendor_data {
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+ u8 config_offset;
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u8 channels;
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bool dualmaster;
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bool nomadik;
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@@ -145,6 +146,7 @@ struct pl08x_bus_data {
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struct pl08x_phy_chan {
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unsigned int id;
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void __iomem *base;
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+ void __iomem *reg_config;
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spinlock_t lock;
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struct pl08x_dma_chan *serving;
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bool locked;
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@@ -334,7 +336,7 @@ static int pl08x_phy_channel_busy(struct pl08x_phy_chan *ch)
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{
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unsigned int val;
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- val = readl(ch->base + PL080_CH_CONFIG);
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+ val = readl(ch->reg_config);
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return val & PL080_CONFIG_ACTIVE;
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}
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@@ -373,7 +375,7 @@ static void pl08x_start_next_txd(struct pl08x_dma_chan *plchan)
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writel(lli->dst, phychan->base + PL080_CH_DST_ADDR);
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writel(lli->lli, phychan->base + PL080_CH_LLI);
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writel(lli->cctl, phychan->base + PL080_CH_CONTROL);
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- writel(txd->ccfg, phychan->base + PL080_CH_CONFIG);
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+ writel(txd->ccfg, phychan->reg_config);
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/* Enable the DMA channel */
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/* Do not access config register until channel shows as disabled */
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@@ -381,11 +383,11 @@ static void pl08x_start_next_txd(struct pl08x_dma_chan *plchan)
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cpu_relax();
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/* Do not access config register until channel shows as inactive */
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- val = readl(phychan->base + PL080_CH_CONFIG);
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+ val = readl(phychan->reg_config);
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while ((val & PL080_CONFIG_ACTIVE) || (val & PL080_CONFIG_ENABLE))
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- val = readl(phychan->base + PL080_CH_CONFIG);
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+ val = readl(phychan->reg_config);
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- writel(val | PL080_CONFIG_ENABLE, phychan->base + PL080_CH_CONFIG);
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+ writel(val | PL080_CONFIG_ENABLE, phychan->reg_config);
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}
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/*
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@@ -404,9 +406,9 @@ static void pl08x_pause_phy_chan(struct pl08x_phy_chan *ch)
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int timeout;
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/* Set the HALT bit and wait for the FIFO to drain */
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- val = readl(ch->base + PL080_CH_CONFIG);
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+ val = readl(ch->reg_config);
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val |= PL080_CONFIG_HALT;
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- writel(val, ch->base + PL080_CH_CONFIG);
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+ writel(val, ch->reg_config);
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/* Wait for channel inactive */
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for (timeout = 1000; timeout; timeout--) {
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@@ -423,9 +425,9 @@ static void pl08x_resume_phy_chan(struct pl08x_phy_chan *ch)
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u32 val;
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/* Clear the HALT bit */
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- val = readl(ch->base + PL080_CH_CONFIG);
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+ val = readl(ch->reg_config);
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val &= ~PL080_CONFIG_HALT;
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- writel(val, ch->base + PL080_CH_CONFIG);
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+ writel(val, ch->reg_config);
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}
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/*
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@@ -437,12 +439,12 @@ static void pl08x_resume_phy_chan(struct pl08x_phy_chan *ch)
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static void pl08x_terminate_phy_chan(struct pl08x_driver_data *pl08x,
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struct pl08x_phy_chan *ch)
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{
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- u32 val = readl(ch->base + PL080_CH_CONFIG);
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+ u32 val = readl(ch->reg_config);
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val &= ~(PL080_CONFIG_ENABLE | PL080_CONFIG_ERR_IRQ_MASK |
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PL080_CONFIG_TC_IRQ_MASK);
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- writel(val, ch->base + PL080_CH_CONFIG);
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+ writel(val, ch->reg_config);
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writel(1 << ch->id, pl08x->base + PL080_ERR_CLEAR);
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writel(1 << ch->id, pl08x->base + PL080_TC_CLEAR);
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@@ -1952,6 +1954,7 @@ static int pl08x_probe(struct amba_device *adev, const struct amba_id *id)
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ch->id = i;
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ch->base = pl08x->base + PL080_Cx_BASE(i);
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+ ch->reg_config = ch->base + vd->config_offset;
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spin_lock_init(&ch->lock);
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/*
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@@ -1962,7 +1965,7 @@ static int pl08x_probe(struct amba_device *adev, const struct amba_id *id)
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if (vd->nomadik) {
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u32 val;
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- val = readl(ch->base + PL080_CH_CONFIG);
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+ val = readl(ch->reg_config);
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if (val & (PL080N_CONFIG_ITPROT | PL080N_CONFIG_SECPROT)) {
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dev_info(&adev->dev, "physical channel %d reserved for secure access only\n", i);
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ch->locked = true;
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@@ -2043,17 +2046,20 @@ out_no_pl08x:
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/* PL080 has 8 channels and the PL080 have just 2 */
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static struct vendor_data vendor_pl080 = {
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+ .config_offset = PL080_CH_CONFIG,
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.channels = 8,
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.dualmaster = true,
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};
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static struct vendor_data vendor_nomadik = {
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+ .config_offset = PL080_CH_CONFIG,
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.channels = 8,
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.dualmaster = true,
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.nomadik = true,
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};
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static struct vendor_data vendor_pl081 = {
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+ .config_offset = PL080_CH_CONFIG,
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.channels = 2,
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.dualmaster = false,
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};
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