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@@ -183,6 +183,44 @@ static struct radeon_asic r300_asic = {
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.ioctl_wait_idle = NULL,
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};
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+
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+static struct radeon_asic r300_asic_pcie = {
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+ .init = &r300_init,
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+ .fini = &r300_fini,
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+ .suspend = &r300_suspend,
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+ .resume = &r300_resume,
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+ .vga_set_state = &r100_vga_set_state,
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+ .gpu_reset = &r300_gpu_reset,
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+ .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
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+ .gart_set_page = &rv370_pcie_gart_set_page,
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+ .cp_commit = &r100_cp_commit,
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+ .ring_start = &r300_ring_start,
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+ .ring_test = &r100_ring_test,
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+ .ring_ib_execute = &r100_ring_ib_execute,
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+ .irq_set = &r100_irq_set,
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+ .irq_process = &r100_irq_process,
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+ .get_vblank_counter = &r100_get_vblank_counter,
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+ .fence_ring_emit = &r300_fence_ring_emit,
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+ .cs_parse = &r300_cs_parse,
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+ .copy_blit = &r100_copy_blit,
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+ .copy_dma = &r200_copy_dma,
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+ .copy = &r100_copy_blit,
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+ .get_engine_clock = &radeon_legacy_get_engine_clock,
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+ .set_engine_clock = &radeon_legacy_set_engine_clock,
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+ .get_memory_clock = &radeon_legacy_get_memory_clock,
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+ .set_memory_clock = NULL,
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+ .set_pcie_lanes = &rv370_set_pcie_lanes,
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+ .set_clock_gating = &radeon_legacy_set_clock_gating,
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+ .set_surface_reg = r100_set_surface_reg,
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+ .clear_surface_reg = r100_clear_surface_reg,
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+ .bandwidth_update = &r100_bandwidth_update,
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+ .hpd_init = &r100_hpd_init,
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+ .hpd_fini = &r100_hpd_fini,
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+ .hpd_sense = &r100_hpd_sense,
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+ .hpd_set_polarity = &r100_hpd_set_polarity,
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+ .ioctl_wait_idle = NULL,
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+};
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+
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/*
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* r420,r423,rv410
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*/
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