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@@ -101,6 +101,8 @@ enum {
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ICH5_PCS = 0x92, /* port control and status */
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PIIX_SCC = 0x0A, /* sub-class code register */
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+ PIIX_FLAG_IGN_PRESENT = (1 << 25), /* ignore PCS present bits */
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+ PIIX_FLAG_SCR = (1 << 26), /* SCR available */
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PIIX_FLAG_AHCI = (1 << 27), /* AHCI possible */
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PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */
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PIIX_FLAG_COMBINED = (1 << 29), /* combined mode possible */
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@@ -314,7 +316,7 @@ static struct ata_port_info piix_port_info[] = {
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{
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.sht = &piix_sht,
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.host_flags = ATA_FLAG_SATA | PIIX_FLAG_COMBINED |
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- PIIX_FLAG_CHECKINTR,
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+ PIIX_FLAG_CHECKINTR | PIIX_FLAG_IGN_PRESENT,
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.pio_mask = 0x1f, /* pio0-4 */
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.mwdma_mask = 0x07, /* mwdma0-2 */
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.udma_mask = 0x7f, /* udma0-6 */
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@@ -325,7 +327,8 @@ static struct ata_port_info piix_port_info[] = {
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{
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.sht = &piix_sht,
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.host_flags = ATA_FLAG_SATA | PIIX_FLAG_COMBINED_ICH6 |
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- PIIX_FLAG_CHECKINTR | ATA_FLAG_SLAVE_POSS,
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+ PIIX_FLAG_CHECKINTR | ATA_FLAG_SLAVE_POSS |
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+ PIIX_FLAG_SCR,
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.pio_mask = 0x1f, /* pio0-4 */
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.mwdma_mask = 0x07, /* mwdma0-2 */
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.udma_mask = 0x7f, /* udma0-6 */
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@@ -337,7 +340,7 @@ static struct ata_port_info piix_port_info[] = {
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.sht = &piix_sht,
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.host_flags = ATA_FLAG_SATA | PIIX_FLAG_COMBINED_ICH6 |
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PIIX_FLAG_CHECKINTR | ATA_FLAG_SLAVE_POSS |
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- PIIX_FLAG_AHCI,
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+ PIIX_FLAG_SCR | PIIX_FLAG_AHCI,
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.pio_mask = 0x1f, /* pio0-4 */
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.mwdma_mask = 0x07, /* mwdma0-2 */
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.udma_mask = 0x7f, /* udma0-6 */
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@@ -349,7 +352,7 @@ static struct ata_port_info piix_port_info[] = {
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.sht = &piix_sht,
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.host_flags = ATA_FLAG_SATA | PIIX_FLAG_COMBINED_ICH6 |
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PIIX_FLAG_CHECKINTR | ATA_FLAG_SLAVE_POSS |
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- PIIX_FLAG_AHCI,
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+ PIIX_FLAG_SCR | PIIX_FLAG_AHCI,
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.pio_mask = 0x1f, /* pio0-4 */
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.mwdma_mask = 0x07, /* mwdma0-2 */
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.udma_mask = 0x7f, /* udma0-6 */
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