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@@ -42,14 +42,14 @@ static unsigned int imx6q_get_speed(unsigned int cpu)
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static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
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{
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- struct cpufreq_freqs freqs;
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struct dev_pm_opp *opp;
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unsigned long freq_hz, volt, volt_old;
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+ unsigned int old_freq, new_freq;
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int ret;
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- freqs.new = freq_table[index].frequency;
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- freq_hz = freqs.new * 1000;
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- freqs.old = clk_get_rate(arm_clk) / 1000;
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+ new_freq = freq_table[index].frequency;
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+ freq_hz = new_freq * 1000;
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+ old_freq = clk_get_rate(arm_clk) / 1000;
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rcu_read_lock();
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opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz);
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@@ -64,26 +64,23 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
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volt_old = regulator_get_voltage(arm_reg);
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dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n",
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- freqs.old / 1000, volt_old / 1000,
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- freqs.new / 1000, volt / 1000);
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-
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- cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);
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+ old_freq / 1000, volt_old / 1000,
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+ new_freq / 1000, volt / 1000);
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/* scaling up? scale voltage before frequency */
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- if (freqs.new > freqs.old) {
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+ if (new_freq > old_freq) {
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ret = regulator_set_voltage_tol(arm_reg, volt, 0);
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if (ret) {
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dev_err(cpu_dev,
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"failed to scale vddarm up: %d\n", ret);
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- freqs.new = freqs.old;
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- goto post_notify;
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+ return ret;
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}
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/*
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* Need to increase vddpu and vddsoc for safety
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* if we are about to run at 1.2 GHz.
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*/
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- if (freqs.new == FREQ_1P2_GHZ / 1000) {
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+ if (new_freq == FREQ_1P2_GHZ / 1000) {
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regulator_set_voltage_tol(pu_reg,
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PU_SOC_VOLTAGE_HIGH, 0);
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regulator_set_voltage_tol(soc_reg,
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@@ -103,21 +100,20 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
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clk_set_parent(step_clk, pll2_pfd2_396m_clk);
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clk_set_parent(pll1_sw_clk, step_clk);
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if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) {
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- clk_set_rate(pll1_sys_clk, freqs.new * 1000);
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+ clk_set_rate(pll1_sys_clk, new_freq * 1000);
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clk_set_parent(pll1_sw_clk, pll1_sys_clk);
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}
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/* Ensure the arm clock divider is what we expect */
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- ret = clk_set_rate(arm_clk, freqs.new * 1000);
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+ ret = clk_set_rate(arm_clk, new_freq * 1000);
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if (ret) {
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dev_err(cpu_dev, "failed to set clock rate: %d\n", ret);
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regulator_set_voltage_tol(arm_reg, volt_old, 0);
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- freqs.new = freqs.old;
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- goto post_notify;
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+ return ret;
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}
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/* scaling down? scale voltage after frequency */
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- if (freqs.new < freqs.old) {
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+ if (new_freq < old_freq) {
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ret = regulator_set_voltage_tol(arm_reg, volt, 0);
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if (ret) {
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dev_warn(cpu_dev,
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@@ -125,7 +121,7 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
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ret = 0;
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}
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- if (freqs.old == FREQ_1P2_GHZ / 1000) {
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+ if (old_freq == FREQ_1P2_GHZ / 1000) {
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regulator_set_voltage_tol(pu_reg,
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PU_SOC_VOLTAGE_NORMAL, 0);
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regulator_set_voltage_tol(soc_reg,
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@@ -133,10 +129,7 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
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}
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}
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-post_notify:
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- cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);
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-
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- return ret;
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+ return 0;
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}
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static int imx6q_cpufreq_init(struct cpufreq_policy *policy)
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