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@@ -507,6 +507,15 @@ static unsigned int ahci_dev_classify(struct ata_port *ap)
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return ata_dev_classify(&tf);
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return ata_dev_classify(&tf);
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}
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}
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+static void ahci_fill_cmd_slot(struct ata_port *ap, u32 opts)
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+{
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+ struct ahci_port_priv *pp = ap->private_data;
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+ pp->cmd_slot[0].opts = cpu_to_le32(opts);
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+ pp->cmd_slot[0].status = 0;
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+ pp->cmd_slot[0].tbl_addr = cpu_to_le32(pp->cmd_tbl_dma & 0xffffffff);
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+ pp->cmd_slot[0].tbl_addr_hi = cpu_to_le32((pp->cmd_tbl_dma >> 16) >> 16);
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+}
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+
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static void ahci_phy_reset(struct ata_port *ap)
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static void ahci_phy_reset(struct ata_port *ap)
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{
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{
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void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
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void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
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@@ -585,42 +594,35 @@ static void ahci_qc_prep(struct ata_queued_cmd *qc)
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{
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{
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struct ata_port *ap = qc->ap;
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struct ata_port *ap = qc->ap;
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struct ahci_port_priv *pp = ap->private_data;
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struct ahci_port_priv *pp = ap->private_data;
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+ int is_atapi = is_atapi_taskfile(&qc->tf);
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u32 opts;
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u32 opts;
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const u32 cmd_fis_len = 5; /* five dwords */
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const u32 cmd_fis_len = 5; /* five dwords */
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unsigned int n_elem;
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unsigned int n_elem;
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- /*
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- * Fill in command slot information (currently only one slot,
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- * slot 0, is currently since we don't do queueing)
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- */
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-
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- opts = cmd_fis_len;
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- if (qc->tf.flags & ATA_TFLAG_WRITE)
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- opts |= AHCI_CMD_WRITE;
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- if (is_atapi_taskfile(&qc->tf))
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- opts |= AHCI_CMD_ATAPI;
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-
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- pp->cmd_slot[0].opts = cpu_to_le32(opts);
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- pp->cmd_slot[0].status = 0;
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- pp->cmd_slot[0].tbl_addr = cpu_to_le32(pp->cmd_tbl_dma & 0xffffffff);
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- pp->cmd_slot[0].tbl_addr_hi = cpu_to_le32((pp->cmd_tbl_dma >> 16) >> 16);
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-
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/*
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/*
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* Fill in command table information. First, the header,
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* Fill in command table information. First, the header,
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* a SATA Register - Host to Device command FIS.
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* a SATA Register - Host to Device command FIS.
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*/
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*/
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ata_tf_to_fis(&qc->tf, pp->cmd_tbl, 0);
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ata_tf_to_fis(&qc->tf, pp->cmd_tbl, 0);
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- if (opts & AHCI_CMD_ATAPI) {
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+ if (is_atapi) {
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memset(pp->cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
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memset(pp->cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
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memcpy(pp->cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, ap->cdb_len);
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memcpy(pp->cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, ap->cdb_len);
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}
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}
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- if (!(qc->flags & ATA_QCFLAG_DMAMAP))
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- return;
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+ n_elem = 0;
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+ if (qc->flags & ATA_QCFLAG_DMAMAP)
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+ n_elem = ahci_fill_sg(qc);
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- n_elem = ahci_fill_sg(qc);
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+ /*
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+ * Fill in command slot information.
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+ */
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+ opts = cmd_fis_len | n_elem << 16;
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+ if (qc->tf.flags & ATA_TFLAG_WRITE)
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+ opts |= AHCI_CMD_WRITE;
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+ if (is_atapi)
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+ opts |= AHCI_CMD_ATAPI;
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- pp->cmd_slot[0].opts |= cpu_to_le32(n_elem << 16);
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+ ahci_fill_cmd_slot(ap, opts);
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}
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}
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static void ahci_restart_port(struct ata_port *ap, u32 irq_stat)
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static void ahci_restart_port(struct ata_port *ap, u32 irq_stat)
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