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@@ -4062,10 +4062,13 @@ static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
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{
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struct b43_phy *phy = &dev->phy;
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struct b43_phy_n *nphy = phy->n;
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+ struct ssb_sprom *sprom = dev->dev->bus_sprom;
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memset(nphy, 0, sizeof(*nphy));
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nphy->hang_avoid = (phy->rev == 3 || phy->rev == 4);
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+ nphy->spur_avoid = (phy->rev >= 3) ?
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+ B43_SPUR_AVOID_AUTO : B43_SPUR_AVOID_DISABLE;
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nphy->gain_boost = true; /* this way we follow wl, assume it is true */
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nphy->txrx_chain = 2; /* sth different than 0 and 1 for now */
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nphy->phyrxchain = 3; /* to avoid b43_nphy_set_rx_core_state like wl */
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@@ -4074,6 +4077,38 @@ static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
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* 0x7f == 127 and we check for 128 when restoring TX pwr ctl. */
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nphy->tx_pwr_idx[0] = 128;
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nphy->tx_pwr_idx[1] = 128;
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+
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+ /* Hardware TX power control and 5GHz power gain */
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+ nphy->txpwrctrl = false;
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+ nphy->pwg_gain_5ghz = false;
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+ if (dev->phy.rev >= 3 ||
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+ (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
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+ (dev->dev->core_rev == 11 || dev->dev->core_rev == 12))) {
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+ nphy->txpwrctrl = true;
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+ nphy->pwg_gain_5ghz = true;
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+ } else if (sprom->revision >= 4) {
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+ if (dev->phy.rev >= 2 &&
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+ (sprom->boardflags2_lo & B43_BFL2_TXPWRCTRL_EN)) {
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+ nphy->txpwrctrl = true;
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+#ifdef CONFIG_B43_SSB
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+ if (dev->dev->bus_type == B43_BUS_SSB &&
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+ dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI) {
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+ struct pci_dev *pdev =
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+ dev->dev->sdev->bus->host_pci;
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+ if (pdev->device == 0x4328 ||
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+ pdev->device == 0x432a)
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+ nphy->pwg_gain_5ghz = true;
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+ }
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+#endif
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+ } else if (sprom->boardflags2_lo & B43_BFL2_5G_PWRGAIN) {
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+ nphy->pwg_gain_5ghz = true;
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+ }
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+ }
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+
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+ if (dev->phy.rev >= 3) {
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+ nphy->ipa2g_on = sprom->fem.ghz2.extpa_gain == 2;
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+ nphy->ipa5g_on = sprom->fem.ghz5.extpa_gain == 2;
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+ }
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}
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static void b43_nphy_op_free(struct b43_wldev *dev)
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