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@@ -683,6 +683,29 @@ nouveau_mem_timing_fini(struct drm_device *dev)
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}
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}
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+int
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+nouveau_mem_vbios_type(struct drm_device *dev)
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+{
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+ struct bit_entry M;
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+ u8 ramcfg = (nv_rd32(dev, 0x101000) & 0x0000003c) >> 2;
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+ if (!bit_table(dev, 'M', &M) || M.version != 2 || M.length < 5) {
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+ u8 *table = ROMPTR(dev, M.data[3]);
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+ if (table && table[0] == 0x10 && ramcfg < table[3]) {
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+ u8 *entry = table + table[1] + (ramcfg * table[2]);
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+ switch (entry[0] & 0x0f) {
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+ case 0: return NV_MEM_TYPE_DDR2;
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+ case 1: return NV_MEM_TYPE_DDR3;
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+ case 2: return NV_MEM_TYPE_GDDR3;
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+ case 3: return NV_MEM_TYPE_GDDR5;
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+ default:
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+ break;
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+ }
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+
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+ }
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+ }
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+ return NV_MEM_TYPE_UNKNOWN;
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+}
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+
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static int
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nouveau_vram_manager_init(struct ttm_mem_type_manager *man, unsigned long psize)
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{
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