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@@ -1409,6 +1409,42 @@ void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active)
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}
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+static void set_primary_clock_state(u8 state)
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+{
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+ u8 value;
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+
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+ switch (state) {
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+ case VIA_STATE_ON:
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+ value = 0x20;
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+ break;
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+ case VIA_STATE_OFF:
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+ value = 0x00;
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+ break;
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+ default:
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+ return;
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+ }
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+
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+ via_write_reg_mask(VIASR, 0x1B, value, 0x30);
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+}
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+
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+static void set_secondary_clock_state(u8 state)
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+{
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+ u8 value;
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+
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+ switch (state) {
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+ case VIA_STATE_ON:
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+ value = 0x80;
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+ break;
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+ case VIA_STATE_OFF:
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+ value = 0x00;
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+ break;
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+ default:
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+ return;
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+ }
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+
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+ via_write_reg_mask(VIASR, 0x1B, value, 0xC0);
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+}
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+
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static void set_primary_pll_state(u8 state)
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{
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u8 value;
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@@ -1442,7 +1478,7 @@ static void set_secondary_pll_state(u8 state)
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return;
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}
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- via_write_reg_mask(VIASR, 0x2D, value, 0x08);
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+ via_write_reg_mask(VIASR, 0x2D, value, 0x0C);
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}
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static u32 cle266_encode_pll(struct pll_config pll)
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