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@@ -1409,6 +1409,42 @@ void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active)
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}
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+static void set_primary_pll_state(u8 state)
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+{
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+ u8 value;
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+
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+ switch (state) {
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+ case VIA_STATE_ON:
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+ value = 0x20;
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+ break;
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+ case VIA_STATE_OFF:
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+ value = 0x00;
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+ break;
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+ default:
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+ return;
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+ }
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+
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+ via_write_reg_mask(VIASR, 0x2D, value, 0x30);
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+}
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+
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+static void set_secondary_pll_state(u8 state)
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+{
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+ u8 value;
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+
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+ switch (state) {
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+ case VIA_STATE_ON:
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+ value = 0x08;
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+ break;
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+ case VIA_STATE_OFF:
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+ value = 0x00;
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+ break;
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+ default:
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+ return;
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+ }
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+
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+ via_write_reg_mask(VIASR, 0x2D, value, 0x08);
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+}
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+
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static u32 cle266_encode_pll(struct pll_config pll)
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{
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return (pll.multiplier << 8)
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@@ -1494,6 +1530,58 @@ static void vx855_set_secondary_pll(struct pll_config config)
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k800_set_secondary_pll_encoded(vx855_encode_pll(config));
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}
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+enum via_clksrc {
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+ VIA_CLKSRC_X1 = 0,
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+ VIA_CLKSRC_TVX1,
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+ VIA_CLKSRC_TVPLL,
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+ VIA_CLKSRC_DVP1TVCLKR,
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+ VIA_CLKSRC_CAP0,
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+ VIA_CLKSRC_CAP1,
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+};
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+
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+static inline u8 set_clock_source_common(enum via_clksrc source, bool use_pll)
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+{
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+ u8 data = 0;
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+
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+ switch (source) {
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+ case VIA_CLKSRC_X1:
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+ data = 0x00;
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+ break;
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+ case VIA_CLKSRC_TVX1:
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+ data = 0x02;
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+ break;
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+ case VIA_CLKSRC_TVPLL:
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+ data = 0x04; /* 0x06 should be the same */
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+ break;
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+ case VIA_CLKSRC_DVP1TVCLKR:
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+ data = 0x0A;
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+ break;
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+ case VIA_CLKSRC_CAP0:
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+ data = 0xC;
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+ break;
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+ case VIA_CLKSRC_CAP1:
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+ data = 0x0E;
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+ break;
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+ }
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+
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+ if (!use_pll)
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+ data |= 1;
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+
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+ return data;
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+}
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+
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+static void set_primary_clock_source(enum via_clksrc source, bool use_pll)
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+{
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+ u8 data = set_clock_source_common(source, use_pll) << 4;
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+ via_write_reg_mask(VIACR, 0x6C, data, 0xF0);
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+}
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+
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+static void set_secondary_clock_source(enum via_clksrc source, bool use_pll)
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+{
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+ u8 data = set_clock_source_common(source, use_pll);
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+ via_write_reg_mask(VIACR, 0x6C, data, 0x0F);
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+}
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+
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static inline u32 get_pll_internal_frequency(u32 ref_freq,
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struct pll_config pll)
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{
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