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@@ -508,25 +508,18 @@ ring_status_page_get_seqno(struct intel_ring_buffer *ring)
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}
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static int
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-ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
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- struct drm_i915_gem_execbuffer2 *exec,
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- struct drm_clip_rect *cliprects,
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- uint64_t exec_offset)
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+ring_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length)
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{
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- uint32_t exec_start;
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int ret;
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- exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
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-
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ret = intel_ring_begin(ring, 2);
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if (ret)
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return ret;
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intel_ring_emit(ring,
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- MI_BATCH_BUFFER_START |
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- (2 << 6) |
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+ MI_BATCH_BUFFER_START | (2 << 6) |
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MI_BATCH_NON_SECURE_I965);
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- intel_ring_emit(ring, exec_start);
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+ intel_ring_emit(ring, offset);
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intel_ring_advance(ring);
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return 0;
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@@ -534,58 +527,40 @@ ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
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static int
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render_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
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- struct drm_i915_gem_execbuffer2 *exec,
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- struct drm_clip_rect *cliprects,
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- uint64_t exec_offset)
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+ u32 offset, u32 len)
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{
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struct drm_device *dev = ring->dev;
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drm_i915_private_t *dev_priv = dev->dev_private;
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- int nbox = exec->num_cliprects;
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- uint32_t exec_start, exec_len;
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- int i, count, ret;
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-
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- exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
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- exec_len = (uint32_t) exec->batch_len;
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+ int ret;
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trace_i915_gem_request_submit(dev, dev_priv->next_seqno + 1);
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- count = nbox ? nbox : 1;
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- for (i = 0; i < count; i++) {
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- if (i < nbox) {
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- ret = i915_emit_box(dev, cliprects, i,
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- exec->DR1, exec->DR4);
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- if (ret)
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- return ret;
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- }
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+ if (IS_I830(dev) || IS_845G(dev)) {
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+ ret = intel_ring_begin(ring, 4);
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+ if (ret)
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+ return ret;
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- if (IS_I830(dev) || IS_845G(dev)) {
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- ret = intel_ring_begin(ring, 4);
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- if (ret)
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- return ret;
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+ intel_ring_emit(ring, MI_BATCH_BUFFER);
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+ intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
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+ intel_ring_emit(ring, offset + len - 8);
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+ intel_ring_emit(ring, 0);
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+ } else {
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+ ret = intel_ring_begin(ring, 2);
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+ if (ret)
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+ return ret;
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- intel_ring_emit(ring, MI_BATCH_BUFFER);
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- intel_ring_emit(ring, exec_start | MI_BATCH_NON_SECURE);
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- intel_ring_emit(ring, exec_start + exec_len - 4);
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- intel_ring_emit(ring, 0);
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+ if (INTEL_INFO(dev)->gen >= 4) {
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+ intel_ring_emit(ring,
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+ MI_BATCH_BUFFER_START | (2 << 6) |
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+ MI_BATCH_NON_SECURE_I965);
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+ intel_ring_emit(ring, offset);
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} else {
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- ret = intel_ring_begin(ring, 2);
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- if (ret)
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- return ret;
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-
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- if (INTEL_INFO(dev)->gen >= 4) {
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- intel_ring_emit(ring,
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- MI_BATCH_BUFFER_START | (2 << 6)
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- | MI_BATCH_NON_SECURE_I965);
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- intel_ring_emit(ring, exec_start);
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- } else {
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- intel_ring_emit(ring, MI_BATCH_BUFFER_START
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- | (2 << 6));
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- intel_ring_emit(ring, exec_start |
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- MI_BATCH_NON_SECURE);
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- }
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+ intel_ring_emit(ring,
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+ MI_BATCH_BUFFER_START | (2 << 6));
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+ intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
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}
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- intel_ring_advance(ring);
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}
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+ intel_ring_advance(ring);
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return 0;
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}
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@@ -904,22 +879,17 @@ static void gen6_ring_flush(struct intel_ring_buffer *ring,
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static int
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gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
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- struct drm_i915_gem_execbuffer2 *exec,
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- struct drm_clip_rect *cliprects,
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- uint64_t exec_offset)
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+ u32 offset, u32 len)
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{
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- uint32_t exec_start;
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int ret;
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- exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
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-
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ret = intel_ring_begin(ring, 2);
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if (ret)
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return ret;
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intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965);
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/* bit0-7 is the length on GEN6+ */
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- intel_ring_emit(ring, exec_start);
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+ intel_ring_emit(ring, offset);
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intel_ring_advance(ring);
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return 0;
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