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@@ -104,6 +104,7 @@ static struct davinci_pcm_dma_params davinci_i2s_pcm_in = {
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struct davinci_mcbsp_dev {
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void __iomem *base;
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+ u32 pcr;
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struct clk *clk;
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struct davinci_pcm_dma_params *dma_params[2];
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};
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@@ -119,17 +120,34 @@ static inline u32 davinci_mcbsp_read_reg(struct davinci_mcbsp_dev *dev, int reg)
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return __raw_readl(dev->base + reg);
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}
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+static void toggle_clock(struct davinci_mcbsp_dev *dev, int playback)
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+{
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+ u32 m = playback ? DAVINCI_MCBSP_PCR_CLKXP : DAVINCI_MCBSP_PCR_CLKRP;
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+ /* The clock needs to toggle to complete reset.
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+ * So, fake it by toggling the clk polarity.
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+ */
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+ davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr ^ m);
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+ davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr);
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+}
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+
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static void davinci_mcbsp_start(struct snd_pcm_substream *substream)
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{
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struct snd_soc_pcm_runtime *rtd = substream->private_data;
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struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
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struct snd_soc_device *socdev = rtd->socdev;
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struct snd_soc_platform *platform = socdev->card->platform;
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+ int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
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u32 spcr;
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int ret;
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-
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- /* Start the sample generator and enable transmitter/receiver */
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+ u32 mask = playback ? DAVINCI_MCBSP_SPCR_XRST : DAVINCI_MCBSP_SPCR_RRST;
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spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
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+ if (spcr & mask) {
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+ /* start off disabled */
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+ davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG,
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+ spcr & ~mask);
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+ toggle_clock(dev, playback);
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+ }
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+ /* Start the sample generator and enable transmitter/receiver */
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spcr |= DAVINCI_MCBSP_SPCR_GRST;
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davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
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@@ -155,6 +173,7 @@ static void davinci_mcbsp_start(struct snd_pcm_substream *substream)
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spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
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spcr &= ~DAVINCI_MCBSP_SPCR_XRST;
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davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
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+ toggle_clock(dev, playback);
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/* Restart the DMA */
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if (platform->pcm_ops->trigger) {
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@@ -188,15 +207,14 @@ static void davinci_mcbsp_stop(struct snd_pcm_substream *substream)
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struct snd_soc_pcm_runtime *rtd = substream->private_data;
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struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
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u32 spcr;
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+ int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
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/* Reset transmitter/receiver and sample rate/frame sync generators */
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spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
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spcr &= ~(DAVINCI_MCBSP_SPCR_GRST | DAVINCI_MCBSP_SPCR_FRST);
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- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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- spcr &= ~DAVINCI_MCBSP_SPCR_XRST;
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- else
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- spcr &= ~DAVINCI_MCBSP_SPCR_RRST;
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+ spcr &= playback ? ~DAVINCI_MCBSP_SPCR_XRST : ~DAVINCI_MCBSP_SPCR_RRST;
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davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
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+ toggle_clock(dev, playback);
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}
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static int davinci_i2s_startup(struct snd_pcm_substream *substream,
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@@ -334,6 +352,7 @@ static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
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return -EINVAL;
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}
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davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr);
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+ dev->pcr = pcr;
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davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, pcr);
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davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, rcr);
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davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, xcr);
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