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@@ -1,5 +1,114 @@
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+#ifndef _AM_X86_MPSPEC_H
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+#define _AM_X86_MPSPEC_H
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+
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+#include <asm/mpspec_def.h>
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+
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#ifdef CONFIG_X86_32
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-# include "mpspec_32.h"
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+#include <mach_mpspec.h>
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+
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+extern int mp_bus_id_to_type[MAX_MP_BUSSES];
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+extern int mp_bus_id_to_node[MAX_MP_BUSSES];
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+extern int mp_bus_id_to_local[MAX_MP_BUSSES];
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+extern int quad_local_to_mp_bus_id[NR_CPUS/4][4];
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+
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+extern unsigned int def_to_bigsmp;
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+extern int apic_version[MAX_APICS];
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+extern int pic_mode;
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+
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#else
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-# include "mpspec_64.h"
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+
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+#define MAX_MP_BUSSES 256
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+/* Each PCI slot may be a combo card with its own bus. 4 IRQ pins per slot. */
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+#define MAX_IRQ_SOURCES (MAX_MP_BUSSES * 4)
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+
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+extern DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
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+
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+#endif
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+
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+extern int mp_bus_id_to_pci_bus[MAX_MP_BUSSES];
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+
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+extern unsigned int boot_cpu_physical_apicid;
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+extern int smp_found_config;
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+extern int nr_ioapics;
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+extern int mp_irq_entries;
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+extern struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
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+extern int mpc_default_type;
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+extern unsigned long mp_lapic_addr;
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+
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+extern void find_smp_config(void);
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+extern void get_smp_config(void);
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+
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+#ifdef CONFIG_ACPI
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+extern void mp_register_lapic(u8 id, u8 enabled);
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+extern void mp_register_lapic_address(u64 address);
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+extern void mp_register_ioapic(u8 id, u32 address, u32 gsi_base);
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+extern void mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger,
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+ u32 gsi);
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+extern void mp_config_acpi_legacy_irqs(void);
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+extern int mp_register_gsi(u32 gsi, int edge_level, int active_high_low);
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+#endif /* CONFIG_ACPI */
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+
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+#define PHYSID_ARRAY_SIZE BITS_TO_LONGS(MAX_APICS)
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+
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+struct physid_mask
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+{
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+ unsigned long mask[PHYSID_ARRAY_SIZE];
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+};
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+
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+typedef struct physid_mask physid_mask_t;
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+
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+#define physid_set(physid, map) set_bit(physid, (map).mask)
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+#define physid_clear(physid, map) clear_bit(physid, (map).mask)
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+#define physid_isset(physid, map) test_bit(physid, (map).mask)
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+#define physid_test_and_set(physid, map) \
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+ test_and_set_bit(physid, (map).mask)
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+
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+#define physids_and(dst, src1, src2) \
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+ bitmap_and((dst).mask, (src1).mask, (src2).mask, MAX_APICS)
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+
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+#define physids_or(dst, src1, src2) \
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+ bitmap_or((dst).mask, (src1).mask, (src2).mask, MAX_APICS)
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+
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+#define physids_clear(map) \
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+ bitmap_zero((map).mask, MAX_APICS)
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+
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+#define physids_complement(dst, src) \
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+ bitmap_complement((dst).mask, (src).mask, MAX_APICS)
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+
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+#define physids_empty(map) \
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+ bitmap_empty((map).mask, MAX_APICS)
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+
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+#define physids_equal(map1, map2) \
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+ bitmap_equal((map1).mask, (map2).mask, MAX_APICS)
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+
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+#define physids_weight(map) \
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+ bitmap_weight((map).mask, MAX_APICS)
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+
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+#define physids_shift_right(d, s, n) \
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+ bitmap_shift_right((d).mask, (s).mask, n, MAX_APICS)
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+
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+#define physids_shift_left(d, s, n) \
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+ bitmap_shift_left((d).mask, (s).mask, n, MAX_APICS)
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+
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+#define physids_coerce(map) ((map).mask[0])
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+
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+#define physids_promote(physids) \
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+ ({ \
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+ physid_mask_t __physid_mask = PHYSID_MASK_NONE; \
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+ __physid_mask.mask[0] = physids; \
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+ __physid_mask; \
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+ })
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+
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+#define physid_mask_of_physid(physid) \
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+ ({ \
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+ physid_mask_t __physid_mask = PHYSID_MASK_NONE; \
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+ physid_set(physid, __physid_mask); \
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+ __physid_mask; \
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+ })
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+
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+#define PHYSID_MASK_ALL { {[0 ... PHYSID_ARRAY_SIZE-1] = ~0UL} }
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+#define PHYSID_MASK_NONE { {[0 ... PHYSID_ARRAY_SIZE-1] = 0UL} }
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+
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+extern physid_mask_t phys_cpu_present_map;
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+
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#endif
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Thomas Gleixner