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@@ -142,25 +142,24 @@ static int gic_set_type(struct irq_data *d, unsigned int type)
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}
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#ifdef CONFIG_SMP
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-static int
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-gic_set_cpu(struct irq_data *d, const struct cpumask *mask_val, bool force)
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+static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
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+ bool force)
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{
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void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3);
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unsigned int shift = (d->irq % 4) * 8;
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unsigned int cpu = cpumask_first(mask_val);
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- u32 val;
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- struct irq_desc *desc;
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+ u32 val, mask, bit;
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- spin_lock(&irq_controller_lock);
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- desc = irq_to_desc(d->irq);
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- if (desc == NULL) {
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- spin_unlock(&irq_controller_lock);
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+ if (cpu >= 8)
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return -EINVAL;
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- }
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+
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+ mask = 0xff << shift;
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+ bit = 1 << (cpu + shift);
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+
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+ spin_lock(&irq_controller_lock);
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d->node = cpu;
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- val = readl(reg) & ~(0xff << shift);
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- val |= 1 << (cpu + shift);
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- writel(val, reg);
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+ val = readl(reg) & ~mask;
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+ writel(val | bit, reg);
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spin_unlock(&irq_controller_lock);
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return 0;
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@@ -203,7 +202,7 @@ static struct irq_chip gic_chip = {
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.irq_unmask = gic_unmask_irq,
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.irq_set_type = gic_set_type,
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#ifdef CONFIG_SMP
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- .irq_set_affinity = gic_set_cpu,
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+ .irq_set_affinity = gic_set_affinity,
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#endif
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};
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