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@@ -0,0 +1,794 @@
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+/*
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+ * Copyright 2010 Advanced Micro Devices, Inc.
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+ *
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+ * Permission is hereby granted, free of charge, to any person obtaining a
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+ * copy of this software and associated documentation files (the "Software"),
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+ * to deal in the Software without restriction, including without limitation
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+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
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+ * and/or sell copies of the Software, and to permit persons to whom the
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+ * Software is furnished to do so, subject to the following conditions:
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+ *
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+ * The above copyright notice and this permission notice shall be included in
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+ * all copies or substantial portions of the Software.
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+ *
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+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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+ * OTHER DEALINGS IN THE SOFTWARE.
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+ *
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+ * Authors: Alex Deucher
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+ */
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+#include <linux/firmware.h>
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+#include <linux/platform_device.h>
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+#include "drmP.h"
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+#include "radeon.h"
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+#include "radeon_drm.h"
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+#include "rv770d.h"
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+#include "atom.h"
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+#include "avivod.h"
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+#include "evergreen_reg.h"
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+
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+static void evergreen_gpu_init(struct radeon_device *rdev);
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+void evergreen_fini(struct radeon_device *rdev);
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+
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+bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
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+{
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+ bool connected = false;
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+ /* XXX */
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+ return connected;
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+}
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+
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+void evergreen_hpd_set_polarity(struct radeon_device *rdev,
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+ enum radeon_hpd_id hpd)
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+{
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+ /* XXX */
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+}
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+
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+void evergreen_hpd_init(struct radeon_device *rdev)
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+{
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+ /* XXX */
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+}
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+
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+
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+void evergreen_bandwidth_update(struct radeon_device *rdev)
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+{
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+ /* XXX */
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+}
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+
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+void evergreen_hpd_fini(struct radeon_device *rdev)
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+{
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+ /* XXX */
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+}
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+
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+static int evergreen_mc_wait_for_idle(struct radeon_device *rdev)
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+{
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+ unsigned i;
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+ u32 tmp;
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+
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+ for (i = 0; i < rdev->usec_timeout; i++) {
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+ /* read MC_STATUS */
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+ tmp = RREG32(SRBM_STATUS) & 0x1F00;
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+ if (!tmp)
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+ return 0;
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+ udelay(1);
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+ }
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+ return -1;
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+}
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+
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+/*
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+ * GART
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+ */
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+int evergreen_pcie_gart_enable(struct radeon_device *rdev)
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+{
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+ u32 tmp;
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+ int r, i;
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+
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+ if (rdev->gart.table.vram.robj == NULL) {
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+ dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
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+ return -EINVAL;
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+ }
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+ r = radeon_gart_table_vram_pin(rdev);
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+ if (r)
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+ return r;
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+ /* Setup L2 cache */
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+ WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
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+ ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
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+ EFFECTIVE_L2_QUEUE_SIZE(7));
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+ WREG32(VM_L2_CNTL2, 0);
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+ WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
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+ /* Setup TLB control */
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+ tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
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+ SYSTEM_ACCESS_MODE_NOT_IN_SYS |
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+ SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
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+ EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
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+ WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
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+ WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
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+ WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
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+ WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
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+ WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
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+ WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
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+ WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
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+ WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
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+ WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
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+ WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
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+ WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
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+ RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
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+ WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
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+ (u32)(rdev->dummy_page.addr >> 12));
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+ for (i = 1; i < 7; i++)
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+ WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
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+
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+ r600_pcie_gart_tlb_flush(rdev);
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+ rdev->gart.ready = true;
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+ return 0;
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+}
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+
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+void evergreen_pcie_gart_disable(struct radeon_device *rdev)
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+{
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+ u32 tmp;
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+ int i, r;
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+
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+ /* Disable all tables */
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+ for (i = 0; i < 7; i++)
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+ WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
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+
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+ /* Setup L2 cache */
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+ WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
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+ EFFECTIVE_L2_QUEUE_SIZE(7));
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+ WREG32(VM_L2_CNTL2, 0);
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+ WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
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+ /* Setup TLB control */
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+ tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
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+ WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
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+ WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
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+ WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
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+ WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
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+ WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
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+ WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
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+ WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
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+ if (rdev->gart.table.vram.robj) {
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+ r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
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+ if (likely(r == 0)) {
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+ radeon_bo_kunmap(rdev->gart.table.vram.robj);
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+ radeon_bo_unpin(rdev->gart.table.vram.robj);
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+ radeon_bo_unreserve(rdev->gart.table.vram.robj);
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+ }
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+ }
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+}
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+
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+void evergreen_pcie_gart_fini(struct radeon_device *rdev)
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+{
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+ evergreen_pcie_gart_disable(rdev);
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+ radeon_gart_table_vram_free(rdev);
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+ radeon_gart_fini(rdev);
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+}
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+
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+
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+void evergreen_agp_enable(struct radeon_device *rdev)
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+{
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+ u32 tmp;
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+ int i;
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+
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+ /* Setup L2 cache */
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+ WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
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+ ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
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+ EFFECTIVE_L2_QUEUE_SIZE(7));
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+ WREG32(VM_L2_CNTL2, 0);
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+ WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
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+ /* Setup TLB control */
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+ tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
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+ SYSTEM_ACCESS_MODE_NOT_IN_SYS |
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+ SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
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+ EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
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+ WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
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+ WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
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+ WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
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+ WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
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+ WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
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+ WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
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+ WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
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+ for (i = 0; i < 7; i++)
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+ WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
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+}
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+
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+static void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
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+{
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+ save->vga_control[0] = RREG32(D1VGA_CONTROL);
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+ save->vga_control[1] = RREG32(D2VGA_CONTROL);
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+ save->vga_control[2] = RREG32(EVERGREEN_D3VGA_CONTROL);
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+ save->vga_control[3] = RREG32(EVERGREEN_D4VGA_CONTROL);
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+ save->vga_control[4] = RREG32(EVERGREEN_D5VGA_CONTROL);
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+ save->vga_control[5] = RREG32(EVERGREEN_D6VGA_CONTROL);
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+ save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
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+ save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
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+ save->crtc_control[0] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
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+ save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
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+ save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
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+ save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
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+ save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
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+ save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
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+
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+ /* Stop all video */
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+ WREG32(VGA_RENDER_CONTROL, 0);
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+ WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
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+ WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
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+ WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
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+ WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
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+ WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
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+ WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
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+ WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
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+ WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
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+ WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
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+ WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
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+ WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
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+ WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
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+ WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
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+ WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
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+ WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
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+ WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
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+ WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
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+ WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
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+
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+ WREG32(D1VGA_CONTROL, 0);
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+ WREG32(D2VGA_CONTROL, 0);
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+ WREG32(EVERGREEN_D3VGA_CONTROL, 0);
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+ WREG32(EVERGREEN_D4VGA_CONTROL, 0);
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+ WREG32(EVERGREEN_D5VGA_CONTROL, 0);
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+ WREG32(EVERGREEN_D6VGA_CONTROL, 0);
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+}
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+
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+static void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
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+{
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+ WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
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+ upper_32_bits(rdev->mc.vram_start));
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+ WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
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+ upper_32_bits(rdev->mc.vram_start));
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+ WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
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+ (u32)rdev->mc.vram_start);
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+ WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
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+ (u32)rdev->mc.vram_start);
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+
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+ WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
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+ upper_32_bits(rdev->mc.vram_start));
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+ WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
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+ upper_32_bits(rdev->mc.vram_start));
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+ WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
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+ (u32)rdev->mc.vram_start);
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+ WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
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+ (u32)rdev->mc.vram_start);
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+
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+ WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
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+ upper_32_bits(rdev->mc.vram_start));
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+ WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
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+ upper_32_bits(rdev->mc.vram_start));
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+ WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
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+ (u32)rdev->mc.vram_start);
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+ WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
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+ (u32)rdev->mc.vram_start);
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+
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+ WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
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+ upper_32_bits(rdev->mc.vram_start));
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+ WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
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+ upper_32_bits(rdev->mc.vram_start));
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+ WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
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+ (u32)rdev->mc.vram_start);
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+ WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
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+ (u32)rdev->mc.vram_start);
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+
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+ WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
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+ upper_32_bits(rdev->mc.vram_start));
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+ WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
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+ upper_32_bits(rdev->mc.vram_start));
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+ WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
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+ (u32)rdev->mc.vram_start);
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+ WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
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+ (u32)rdev->mc.vram_start);
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+
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+ WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
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+ upper_32_bits(rdev->mc.vram_start));
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+ WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
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+ upper_32_bits(rdev->mc.vram_start));
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+ WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
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+ (u32)rdev->mc.vram_start);
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+ WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
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|
|
+ (u32)rdev->mc.vram_start);
|
|
|
+
|
|
|
+ WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
|
|
|
+ WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
|
|
|
+ /* Unlock host access */
|
|
|
+ WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
|
|
|
+ mdelay(1);
|
|
|
+ /* Restore video state */
|
|
|
+ WREG32(D1VGA_CONTROL, save->vga_control[0]);
|
|
|
+ WREG32(D2VGA_CONTROL, save->vga_control[1]);
|
|
|
+ WREG32(EVERGREEN_D3VGA_CONTROL, save->vga_control[2]);
|
|
|
+ WREG32(EVERGREEN_D4VGA_CONTROL, save->vga_control[3]);
|
|
|
+ WREG32(EVERGREEN_D5VGA_CONTROL, save->vga_control[4]);
|
|
|
+ WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]);
|
|
|
+ WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
|
|
|
+ WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
|
|
|
+ WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
|
|
|
+ WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
|
|
|
+ WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
|
|
|
+ WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
|
|
|
+ WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, save->crtc_control[0]);
|
|
|
+ WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, save->crtc_control[1]);
|
|
|
+ WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]);
|
|
|
+ WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]);
|
|
|
+ WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]);
|
|
|
+ WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]);
|
|
|
+ WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
|
|
|
+ WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
|
|
|
+ WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
|
|
|
+ WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
|
|
|
+ WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
|
|
|
+ WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
|
|
|
+ WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
|
|
|
+}
|
|
|
+
|
|
|
+static void evergreen_mc_program(struct radeon_device *rdev)
|
|
|
+{
|
|
|
+ struct evergreen_mc_save save;
|
|
|
+ u32 tmp;
|
|
|
+ int i, j;
|
|
|
+
|
|
|
+ /* Initialize HDP */
|
|
|
+ for (i = 0, j = 0; i < 32; i++, j += 0x18) {
|
|
|
+ WREG32((0x2c14 + j), 0x00000000);
|
|
|
+ WREG32((0x2c18 + j), 0x00000000);
|
|
|
+ WREG32((0x2c1c + j), 0x00000000);
|
|
|
+ WREG32((0x2c20 + j), 0x00000000);
|
|
|
+ WREG32((0x2c24 + j), 0x00000000);
|
|
|
+ }
|
|
|
+ WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
|
|
|
+
|
|
|
+ evergreen_mc_stop(rdev, &save);
|
|
|
+ if (evergreen_mc_wait_for_idle(rdev)) {
|
|
|
+ dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
|
|
|
+ }
|
|
|
+ /* Lockout access through VGA aperture*/
|
|
|
+ WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
|
|
|
+ /* Update configuration */
|
|
|
+ if (rdev->flags & RADEON_IS_AGP) {
|
|
|
+ if (rdev->mc.vram_start < rdev->mc.gtt_start) {
|
|
|
+ /* VRAM before AGP */
|
|
|
+ WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
|
|
|
+ rdev->mc.vram_start >> 12);
|
|
|
+ WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
|
|
|
+ rdev->mc.gtt_end >> 12);
|
|
|
+ } else {
|
|
|
+ /* VRAM after AGP */
|
|
|
+ WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
|
|
|
+ rdev->mc.gtt_start >> 12);
|
|
|
+ WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
|
|
|
+ rdev->mc.vram_end >> 12);
|
|
|
+ }
|
|
|
+ } else {
|
|
|
+ WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
|
|
|
+ rdev->mc.vram_start >> 12);
|
|
|
+ WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
|
|
|
+ rdev->mc.vram_end >> 12);
|
|
|
+ }
|
|
|
+ WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
|
|
|
+ tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
|
|
|
+ tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
|
|
|
+ WREG32(MC_VM_FB_LOCATION, tmp);
|
|
|
+ WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
|
|
|
+ WREG32(HDP_NONSURFACE_INFO, (2 << 7));
|
|
|
+ WREG32(HDP_NONSURFACE_SIZE, (rdev->mc.mc_vram_size - 1) | 0x3FF);
|
|
|
+ if (rdev->flags & RADEON_IS_AGP) {
|
|
|
+ WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
|
|
|
+ WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
|
|
|
+ WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
|
|
|
+ } else {
|
|
|
+ WREG32(MC_VM_AGP_BASE, 0);
|
|
|
+ WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
|
|
|
+ WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
|
|
|
+ }
|
|
|
+ if (evergreen_mc_wait_for_idle(rdev)) {
|
|
|
+ dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
|
|
|
+ }
|
|
|
+ evergreen_mc_resume(rdev, &save);
|
|
|
+ /* we need to own VRAM, so turn off the VGA renderer here
|
|
|
+ * to stop it overwriting our objects */
|
|
|
+ rv515_vga_render_disable(rdev);
|
|
|
+}
|
|
|
+
|
|
|
+#if 0
|
|
|
+/*
|
|
|
+ * CP.
|
|
|
+ */
|
|
|
+static void evergreen_cp_stop(struct radeon_device *rdev)
|
|
|
+{
|
|
|
+ /* XXX */
|
|
|
+}
|
|
|
+
|
|
|
+
|
|
|
+static int evergreen_cp_load_microcode(struct radeon_device *rdev)
|
|
|
+{
|
|
|
+ /* XXX */
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+
|
|
|
+/*
|
|
|
+ * Core functions
|
|
|
+ */
|
|
|
+static u32 evergreen_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
|
|
|
+ u32 num_backends,
|
|
|
+ u32 backend_disable_mask)
|
|
|
+{
|
|
|
+ u32 backend_map = 0;
|
|
|
+
|
|
|
+ return backend_map;
|
|
|
+}
|
|
|
+#endif
|
|
|
+
|
|
|
+static void evergreen_gpu_init(struct radeon_device *rdev)
|
|
|
+{
|
|
|
+ /* XXX */
|
|
|
+}
|
|
|
+
|
|
|
+int evergreen_mc_init(struct radeon_device *rdev)
|
|
|
+{
|
|
|
+ fixed20_12 a;
|
|
|
+ u32 tmp;
|
|
|
+ int chansize, numchan;
|
|
|
+ int r;
|
|
|
+
|
|
|
+ /* Get VRAM informations */
|
|
|
+ rdev->mc.vram_is_ddr = true;
|
|
|
+ tmp = RREG32(MC_ARB_RAMCFG);
|
|
|
+ if (tmp & CHANSIZE_OVERRIDE) {
|
|
|
+ chansize = 16;
|
|
|
+ } else if (tmp & CHANSIZE_MASK) {
|
|
|
+ chansize = 64;
|
|
|
+ } else {
|
|
|
+ chansize = 32;
|
|
|
+ }
|
|
|
+ tmp = RREG32(MC_SHARED_CHMAP);
|
|
|
+ switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
|
|
|
+ case 0:
|
|
|
+ default:
|
|
|
+ numchan = 1;
|
|
|
+ break;
|
|
|
+ case 1:
|
|
|
+ numchan = 2;
|
|
|
+ break;
|
|
|
+ case 2:
|
|
|
+ numchan = 4;
|
|
|
+ break;
|
|
|
+ case 3:
|
|
|
+ numchan = 8;
|
|
|
+ break;
|
|
|
+ }
|
|
|
+ rdev->mc.vram_width = numchan * chansize;
|
|
|
+ /* Could aper size report 0 ? */
|
|
|
+ rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
|
|
|
+ rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
|
|
|
+ /* Setup GPU memory space */
|
|
|
+ /* size in MB on evergreen */
|
|
|
+ rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
|
|
|
+ rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
|
|
|
+
|
|
|
+ if (rdev->mc.mc_vram_size > rdev->mc.aper_size)
|
|
|
+ rdev->mc.mc_vram_size = rdev->mc.aper_size;
|
|
|
+
|
|
|
+ if (rdev->mc.real_vram_size > rdev->mc.aper_size)
|
|
|
+ rdev->mc.real_vram_size = rdev->mc.aper_size;
|
|
|
+
|
|
|
+ if (rdev->flags & RADEON_IS_AGP) {
|
|
|
+ r = radeon_agp_init(rdev);
|
|
|
+ if (r)
|
|
|
+ return r;
|
|
|
+ /* gtt_size is setup by radeon_agp_init */
|
|
|
+ rdev->mc.gtt_location = rdev->mc.agp_base;
|
|
|
+ tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size;
|
|
|
+ /* Try to put vram before or after AGP because we
|
|
|
+ * we want SYSTEM_APERTURE to cover both VRAM and
|
|
|
+ * AGP so that GPU can catch out of VRAM/AGP access
|
|
|
+ */
|
|
|
+ if (rdev->mc.gtt_location > rdev->mc.mc_vram_size) {
|
|
|
+ /* Enought place before */
|
|
|
+ rdev->mc.vram_location = rdev->mc.gtt_location -
|
|
|
+ rdev->mc.mc_vram_size;
|
|
|
+ } else if (tmp > rdev->mc.mc_vram_size) {
|
|
|
+ /* Enought place after */
|
|
|
+ rdev->mc.vram_location = rdev->mc.gtt_location +
|
|
|
+ rdev->mc.gtt_size;
|
|
|
+ } else {
|
|
|
+ /* Try to setup VRAM then AGP might not
|
|
|
+ * not work on some card
|
|
|
+ */
|
|
|
+ rdev->mc.vram_location = 0x00000000UL;
|
|
|
+ rdev->mc.gtt_location = rdev->mc.mc_vram_size;
|
|
|
+ }
|
|
|
+ } else {
|
|
|
+ rdev->mc.vram_location = 0x00000000UL;
|
|
|
+ rdev->mc.gtt_location = rdev->mc.mc_vram_size;
|
|
|
+ rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
|
|
|
+ }
|
|
|
+ rdev->mc.vram_start = rdev->mc.vram_location;
|
|
|
+ rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
|
|
|
+ rdev->mc.gtt_start = rdev->mc.gtt_location;
|
|
|
+ rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
|
|
|
+ /* FIXME: we should enforce default clock in case GPU is not in
|
|
|
+ * default setup
|
|
|
+ */
|
|
|
+ a.full = rfixed_const(100);
|
|
|
+ rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
|
|
|
+ rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+int evergreen_gpu_reset(struct radeon_device *rdev)
|
|
|
+{
|
|
|
+ /* FIXME: implement for evergreen */
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static int evergreen_startup(struct radeon_device *rdev)
|
|
|
+{
|
|
|
+#if 0
|
|
|
+ int r;
|
|
|
+
|
|
|
+ if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
|
|
|
+ r = r600_init_microcode(rdev);
|
|
|
+ if (r) {
|
|
|
+ DRM_ERROR("Failed to load firmware!\n");
|
|
|
+ return r;
|
|
|
+ }
|
|
|
+ }
|
|
|
+#endif
|
|
|
+ evergreen_mc_program(rdev);
|
|
|
+#if 0
|
|
|
+ if (rdev->flags & RADEON_IS_AGP) {
|
|
|
+ evergreem_agp_enable(rdev);
|
|
|
+ } else {
|
|
|
+ r = evergreen_pcie_gart_enable(rdev);
|
|
|
+ if (r)
|
|
|
+ return r;
|
|
|
+ }
|
|
|
+#endif
|
|
|
+ evergreen_gpu_init(rdev);
|
|
|
+#if 0
|
|
|
+ if (!rdev->r600_blit.shader_obj) {
|
|
|
+ r = r600_blit_init(rdev);
|
|
|
+ if (r) {
|
|
|
+ DRM_ERROR("radeon: failed blitter (%d).\n", r);
|
|
|
+ return r;
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
|
|
|
+ if (unlikely(r != 0))
|
|
|
+ return r;
|
|
|
+ r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
|
|
|
+ &rdev->r600_blit.shader_gpu_addr);
|
|
|
+ radeon_bo_unreserve(rdev->r600_blit.shader_obj);
|
|
|
+ if (r) {
|
|
|
+ DRM_ERROR("failed to pin blit object %d\n", r);
|
|
|
+ return r;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Enable IRQ */
|
|
|
+ r = r600_irq_init(rdev);
|
|
|
+ if (r) {
|
|
|
+ DRM_ERROR("radeon: IH init failed (%d).\n", r);
|
|
|
+ radeon_irq_kms_fini(rdev);
|
|
|
+ return r;
|
|
|
+ }
|
|
|
+ r600_irq_set(rdev);
|
|
|
+
|
|
|
+ r = radeon_ring_init(rdev, rdev->cp.ring_size);
|
|
|
+ if (r)
|
|
|
+ return r;
|
|
|
+ r = evergreen_cp_load_microcode(rdev);
|
|
|
+ if (r)
|
|
|
+ return r;
|
|
|
+ r = r600_cp_resume(rdev);
|
|
|
+ if (r)
|
|
|
+ return r;
|
|
|
+ /* write back buffer are not vital so don't worry about failure */
|
|
|
+ r600_wb_enable(rdev);
|
|
|
+#endif
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+int evergreen_resume(struct radeon_device *rdev)
|
|
|
+{
|
|
|
+ int r;
|
|
|
+
|
|
|
+ /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
|
|
|
+ * posting will perform necessary task to bring back GPU into good
|
|
|
+ * shape.
|
|
|
+ */
|
|
|
+ /* post card */
|
|
|
+ atom_asic_init(rdev->mode_info.atom_context);
|
|
|
+ /* Initialize clocks */
|
|
|
+ r = radeon_clocks_init(rdev);
|
|
|
+ if (r) {
|
|
|
+ return r;
|
|
|
+ }
|
|
|
+
|
|
|
+ r = evergreen_startup(rdev);
|
|
|
+ if (r) {
|
|
|
+ DRM_ERROR("r600 startup failed on resume\n");
|
|
|
+ return r;
|
|
|
+ }
|
|
|
+#if 0
|
|
|
+ r = r600_ib_test(rdev);
|
|
|
+ if (r) {
|
|
|
+ DRM_ERROR("radeon: failled testing IB (%d).\n", r);
|
|
|
+ return r;
|
|
|
+ }
|
|
|
+#endif
|
|
|
+ return r;
|
|
|
+
|
|
|
+}
|
|
|
+
|
|
|
+int evergreen_suspend(struct radeon_device *rdev)
|
|
|
+{
|
|
|
+#if 0
|
|
|
+ int r;
|
|
|
+
|
|
|
+ /* FIXME: we should wait for ring to be empty */
|
|
|
+ r700_cp_stop(rdev);
|
|
|
+ rdev->cp.ready = false;
|
|
|
+ r600_wb_disable(rdev);
|
|
|
+ evergreen_pcie_gart_disable(rdev);
|
|
|
+ /* unpin shaders bo */
|
|
|
+ r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
|
|
|
+ if (likely(r == 0)) {
|
|
|
+ radeon_bo_unpin(rdev->r600_blit.shader_obj);
|
|
|
+ radeon_bo_unreserve(rdev->r600_blit.shader_obj);
|
|
|
+ }
|
|
|
+#endif
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static bool evergreen_card_posted(struct radeon_device *rdev)
|
|
|
+{
|
|
|
+ u32 reg;
|
|
|
+
|
|
|
+ /* first check CRTCs */
|
|
|
+ reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
|
|
|
+ RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) |
|
|
|
+ RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
|
|
|
+ RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) |
|
|
|
+ RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
|
|
|
+ RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
|
|
|
+ if (reg & EVERGREEN_CRTC_MASTER_EN)
|
|
|
+ return true;
|
|
|
+
|
|
|
+ /* then check MEM_SIZE, in case the crtcs are off */
|
|
|
+ if (RREG32(CONFIG_MEMSIZE))
|
|
|
+ return true;
|
|
|
+
|
|
|
+ return false;
|
|
|
+}
|
|
|
+
|
|
|
+/* Plan is to move initialization in that function and use
|
|
|
+ * helper function so that radeon_device_init pretty much
|
|
|
+ * do nothing more than calling asic specific function. This
|
|
|
+ * should also allow to remove a bunch of callback function
|
|
|
+ * like vram_info.
|
|
|
+ */
|
|
|
+int evergreen_init(struct radeon_device *rdev)
|
|
|
+{
|
|
|
+ int r;
|
|
|
+
|
|
|
+ r = radeon_dummy_page_init(rdev);
|
|
|
+ if (r)
|
|
|
+ return r;
|
|
|
+ /* This don't do much */
|
|
|
+ r = radeon_gem_init(rdev);
|
|
|
+ if (r)
|
|
|
+ return r;
|
|
|
+ /* Read BIOS */
|
|
|
+ if (!radeon_get_bios(rdev)) {
|
|
|
+ if (ASIC_IS_AVIVO(rdev))
|
|
|
+ return -EINVAL;
|
|
|
+ }
|
|
|
+ /* Must be an ATOMBIOS */
|
|
|
+ if (!rdev->is_atom_bios) {
|
|
|
+ dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
|
|
|
+ return -EINVAL;
|
|
|
+ }
|
|
|
+ r = radeon_atombios_init(rdev);
|
|
|
+ if (r)
|
|
|
+ return r;
|
|
|
+ /* Post card if necessary */
|
|
|
+ if (!evergreen_card_posted(rdev)) {
|
|
|
+ if (!rdev->bios) {
|
|
|
+ dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
|
|
|
+ return -EINVAL;
|
|
|
+ }
|
|
|
+ DRM_INFO("GPU not posted. posting now...\n");
|
|
|
+ atom_asic_init(rdev->mode_info.atom_context);
|
|
|
+ }
|
|
|
+ /* Initialize scratch registers */
|
|
|
+ r600_scratch_init(rdev);
|
|
|
+ /* Initialize surface registers */
|
|
|
+ radeon_surface_init(rdev);
|
|
|
+ /* Initialize clocks */
|
|
|
+ radeon_get_clock_info(rdev->ddev);
|
|
|
+ r = radeon_clocks_init(rdev);
|
|
|
+ if (r)
|
|
|
+ return r;
|
|
|
+ /* Initialize power management */
|
|
|
+ radeon_pm_init(rdev);
|
|
|
+ /* Fence driver */
|
|
|
+ r = radeon_fence_driver_init(rdev);
|
|
|
+ if (r)
|
|
|
+ return r;
|
|
|
+ r = evergreen_mc_init(rdev);
|
|
|
+ if (r)
|
|
|
+ return r;
|
|
|
+ /* Memory manager */
|
|
|
+ r = radeon_bo_init(rdev);
|
|
|
+ if (r)
|
|
|
+ return r;
|
|
|
+#if 0
|
|
|
+ r = radeon_irq_kms_init(rdev);
|
|
|
+ if (r)
|
|
|
+ return r;
|
|
|
+
|
|
|
+ rdev->cp.ring_obj = NULL;
|
|
|
+ r600_ring_init(rdev, 1024 * 1024);
|
|
|
+
|
|
|
+ rdev->ih.ring_obj = NULL;
|
|
|
+ r600_ih_ring_init(rdev, 64 * 1024);
|
|
|
+
|
|
|
+ r = r600_pcie_gart_init(rdev);
|
|
|
+ if (r)
|
|
|
+ return r;
|
|
|
+#endif
|
|
|
+ rdev->accel_working = false;
|
|
|
+ r = evergreen_startup(rdev);
|
|
|
+ if (r) {
|
|
|
+ evergreen_suspend(rdev);
|
|
|
+ /*r600_wb_fini(rdev);*/
|
|
|
+ /*radeon_ring_fini(rdev);*/
|
|
|
+ /*evergreen_pcie_gart_fini(rdev);*/
|
|
|
+ rdev->accel_working = false;
|
|
|
+ }
|
|
|
+ if (rdev->accel_working) {
|
|
|
+ r = radeon_ib_pool_init(rdev);
|
|
|
+ if (r) {
|
|
|
+ DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r);
|
|
|
+ rdev->accel_working = false;
|
|
|
+ }
|
|
|
+ r = r600_ib_test(rdev);
|
|
|
+ if (r) {
|
|
|
+ DRM_ERROR("radeon: failed testing IB (%d).\n", r);
|
|
|
+ rdev->accel_working = false;
|
|
|
+ }
|
|
|
+ }
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+void evergreen_fini(struct radeon_device *rdev)
|
|
|
+{
|
|
|
+ evergreen_suspend(rdev);
|
|
|
+#if 0
|
|
|
+ r600_blit_fini(rdev);
|
|
|
+ r600_irq_fini(rdev);
|
|
|
+ radeon_irq_kms_fini(rdev);
|
|
|
+ radeon_ring_fini(rdev);
|
|
|
+ r600_wb_fini(rdev);
|
|
|
+ evergreen_pcie_gart_fini(rdev);
|
|
|
+#endif
|
|
|
+ radeon_gem_fini(rdev);
|
|
|
+ radeon_fence_driver_fini(rdev);
|
|
|
+ radeon_clocks_fini(rdev);
|
|
|
+ radeon_agp_fini(rdev);
|
|
|
+ radeon_bo_fini(rdev);
|
|
|
+ radeon_atombios_fini(rdev);
|
|
|
+ kfree(rdev->bios);
|
|
|
+ rdev->bios = NULL;
|
|
|
+ radeon_dummy_page_fini(rdev);
|
|
|
+}
|
Alex Deucher