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@@ -3390,6 +3390,203 @@ static void free_hba(int i)
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kfree(p);
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}
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+/* Send a message CDB to the firmware. */
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+static __devinit int cciss_message(struct pci_dev *pdev, unsigned char opcode, unsigned char type)
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+{
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+ typedef struct {
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+ CommandListHeader_struct CommandHeader;
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+ RequestBlock_struct Request;
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+ ErrDescriptor_struct ErrorDescriptor;
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+ } Command;
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+ static const size_t cmd_sz = sizeof(Command) + sizeof(ErrorInfo_struct);
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+ Command *cmd;
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+ dma_addr_t paddr64;
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+ uint32_t paddr32, tag;
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+ void __iomem *vaddr;
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+ int i, err;
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+
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+ vaddr = ioremap_nocache(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0));
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+ if (vaddr == NULL)
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+ return -ENOMEM;
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+
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+ /* The Inbound Post Queue only accepts 32-bit physical addresses for the
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+ CCISS commands, so they must be allocated from the lower 4GiB of
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+ memory. */
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+ err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
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+ if (err) {
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+ iounmap(vaddr);
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+ return -ENOMEM;
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+ }
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+
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+ cmd = pci_alloc_consistent(pdev, cmd_sz, &paddr64);
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+ if (cmd == NULL) {
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+ iounmap(vaddr);
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+ return -ENOMEM;
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+ }
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+
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+ /* This must fit, because of the 32-bit consistent DMA mask. Also,
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+ although there's no guarantee, we assume that the address is at
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+ least 4-byte aligned (most likely, it's page-aligned). */
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+ paddr32 = paddr64;
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+
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+ cmd->CommandHeader.ReplyQueue = 0;
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+ cmd->CommandHeader.SGList = 0;
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+ cmd->CommandHeader.SGTotal = 0;
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+ cmd->CommandHeader.Tag.lower = paddr32;
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+ cmd->CommandHeader.Tag.upper = 0;
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+ memset(&cmd->CommandHeader.LUN.LunAddrBytes, 0, 8);
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+
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+ cmd->Request.CDBLen = 16;
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+ cmd->Request.Type.Type = TYPE_MSG;
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+ cmd->Request.Type.Attribute = ATTR_HEADOFQUEUE;
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+ cmd->Request.Type.Direction = XFER_NONE;
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+ cmd->Request.Timeout = 0; /* Don't time out */
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+ cmd->Request.CDB[0] = opcode;
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+ cmd->Request.CDB[1] = type;
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+ memset(&cmd->Request.CDB[2], 0, 14); /* the rest of the CDB is reserved */
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+
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+ cmd->ErrorDescriptor.Addr.lower = paddr32 + sizeof(Command);
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+ cmd->ErrorDescriptor.Addr.upper = 0;
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+ cmd->ErrorDescriptor.Len = sizeof(ErrorInfo_struct);
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+
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+ writel(paddr32, vaddr + SA5_REQUEST_PORT_OFFSET);
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+
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+ for (i = 0; i < 10; i++) {
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+ tag = readl(vaddr + SA5_REPLY_PORT_OFFSET);
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+ if ((tag & ~3) == paddr32)
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+ break;
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+ schedule_timeout_uninterruptible(HZ);
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+ }
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+
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+ iounmap(vaddr);
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+
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+ /* we leak the DMA buffer here ... no choice since the controller could
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+ still complete the command. */
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+ if (i == 10) {
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+ printk(KERN_ERR "cciss: controller message %02x:%02x timed out\n",
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+ opcode, type);
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+ return -ETIMEDOUT;
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+ }
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+
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+ pci_free_consistent(pdev, cmd_sz, cmd, paddr64);
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+
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+ if (tag & 2) {
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+ printk(KERN_ERR "cciss: controller message %02x:%02x failed\n",
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+ opcode, type);
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+ return -EIO;
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+ }
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+
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+ printk(KERN_INFO "cciss: controller message %02x:%02x succeeded\n",
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+ opcode, type);
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+ return 0;
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+}
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+
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+#define cciss_soft_reset_controller(p) cciss_message(p, 1, 0)
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+#define cciss_noop(p) cciss_message(p, 3, 0)
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+
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+static __devinit int cciss_reset_msi(struct pci_dev *pdev)
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+{
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+/* the #defines are stolen from drivers/pci/msi.h. */
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+#define msi_control_reg(base) (base + PCI_MSI_FLAGS)
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+#define PCI_MSIX_FLAGS_ENABLE (1 << 15)
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+
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+ int pos;
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+ u16 control = 0;
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+
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+ pos = pci_find_capability(pdev, PCI_CAP_ID_MSI);
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+ if (pos) {
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+ pci_read_config_word(pdev, msi_control_reg(pos), &control);
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+ if (control & PCI_MSI_FLAGS_ENABLE) {
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+ printk(KERN_INFO "cciss: resetting MSI\n");
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+ pci_write_config_word(pdev, msi_control_reg(pos), control & ~PCI_MSI_FLAGS_ENABLE);
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+ }
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+ }
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+
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+ pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
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+ if (pos) {
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+ pci_read_config_word(pdev, msi_control_reg(pos), &control);
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+ if (control & PCI_MSIX_FLAGS_ENABLE) {
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+ printk(KERN_INFO "cciss: resetting MSI-X\n");
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+ pci_write_config_word(pdev, msi_control_reg(pos), control & ~PCI_MSIX_FLAGS_ENABLE);
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+ }
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+ }
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+
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+ return 0;
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+}
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+
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+/* This does a hard reset of the controller using PCI power management
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+ * states. */
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+static __devinit int cciss_hard_reset_controller(struct pci_dev *pdev)
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+{
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+ u16 pmcsr, saved_config_space[32];
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+ int i, pos;
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+
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+ printk(KERN_INFO "cciss: using PCI PM to reset controller\n");
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+
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+ /* This is very nearly the same thing as
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+
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+ pci_save_state(pci_dev);
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+ pci_set_power_state(pci_dev, PCI_D3hot);
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+ pci_set_power_state(pci_dev, PCI_D0);
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+ pci_restore_state(pci_dev);
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+
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+ but we can't use these nice canned kernel routines on
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+ kexec, because they also check the MSI/MSI-X state in PCI
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+ configuration space and do the wrong thing when it is
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+ set/cleared. Also, the pci_save/restore_state functions
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+ violate the ordering requirements for restoring the
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+ configuration space from the CCISS document (see the
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+ comment below). So we roll our own .... */
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+
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+ for (i = 0; i < 32; i++)
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+ pci_read_config_word(pdev, 2*i, &saved_config_space[i]);
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+
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+ pos = pci_find_capability(pdev, PCI_CAP_ID_PM);
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+ if (pos == 0) {
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+ printk(KERN_ERR "cciss_reset_controller: PCI PM not supported\n");
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+ return -ENODEV;
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+ }
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+
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+ /* Quoting from the Open CISS Specification: "The Power
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+ * Management Control/Status Register (CSR) controls the power
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+ * state of the device. The normal operating state is D0,
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+ * CSR=00h. The software off state is D3, CSR=03h. To reset
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+ * the controller, place the interface device in D3 then to
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+ * D0, this causes a secondary PCI reset which will reset the
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+ * controller." */
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+
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+ /* enter the D3hot power management state */
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+ pci_read_config_word(pdev, pos + PCI_PM_CTRL, &pmcsr);
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+ pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
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+ pmcsr |= PCI_D3hot;
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+ pci_write_config_word(pdev, pos + PCI_PM_CTRL, pmcsr);
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+
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+ schedule_timeout_uninterruptible(HZ >> 1);
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+
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+ /* enter the D0 power management state */
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+ pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
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+ pmcsr |= PCI_D0;
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+ pci_write_config_word(pdev, pos + PCI_PM_CTRL, pmcsr);
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+
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+ schedule_timeout_uninterruptible(HZ >> 1);
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+
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+ /* Restore the PCI configuration space. The Open CISS
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+ * Specification says, "Restore the PCI Configuration
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+ * Registers, offsets 00h through 60h. It is important to
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+ * restore the command register, 16-bits at offset 04h,
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+ * last. Do not restore the configuration status register,
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+ * 16-bits at offset 06h." Note that the offset is 2*i. */
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+ for (i = 0; i < 32; i++) {
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+ if (i == 2 || i == 3)
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+ continue;
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+ pci_write_config_word(pdev, 2*i, saved_config_space[i]);
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+ }
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+ wmb();
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+ pci_write_config_word(pdev, 4, saved_config_space[2]);
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+
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+ return 0;
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+}
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+
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/*
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* This is it. Find all the controllers and register them. I really hate
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* stealing all these major device numbers.
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@@ -3404,6 +3601,24 @@ static int __devinit cciss_init_one(struct pci_dev *pdev,
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int dac, return_code;
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InquiryData_struct *inq_buff = NULL;
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+ if (reset_devices) {
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+ /* Reset the controller with a PCI power-cycle */
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+ if (cciss_hard_reset_controller(pdev) || cciss_reset_msi(pdev))
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+ return -ENODEV;
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+
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+ /* Some devices (notably the HP Smart Array 5i Controller)
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+ need a little pause here */
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+ schedule_timeout_uninterruptible(30*HZ);
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+
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+ /* Now try to get the controller to respond to a no-op */
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+ for (i=0; i<12; i++) {
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+ if (cciss_noop(pdev) == 0)
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+ break;
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+ else
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+ printk("cciss: no-op failed%s\n", (i < 11 ? "; re-trying" : ""));
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+ }
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+ }
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+
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i = alloc_cciss_hba();
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if (i < 0)
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return -1;
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Linus Torvalds