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@@ -55,6 +55,7 @@
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#define VS30 (1 << 25)
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#define SDVS18 (0x5 << 9)
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#define SDVS30 (0x6 << 9)
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+#define SDVS33 (0x7 << 9)
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#define SDVSCLR 0xFFFFF1FF
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#define SDVSDET 0x00000400
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#define AUTOIDLE 0x1
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@@ -375,6 +376,32 @@ static void mmc_omap_report_irq(struct mmc_omap_host *host, u32 status)
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}
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#endif /* CONFIG_MMC_DEBUG */
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+/*
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+ * MMC controller internal state machines reset
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+ *
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+ * Used to reset command or data internal state machines, using respectively
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+ * SRC or SRD bit of SYSCTL register
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+ * Can be called from interrupt context
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+ */
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+static inline void mmc_omap_reset_controller_fsm(struct mmc_omap_host *host,
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+ unsigned long bit)
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+{
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+ unsigned long i = 0;
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+ unsigned long limit = (loops_per_jiffy *
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+ msecs_to_jiffies(MMC_TIMEOUT_MS));
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+
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+ OMAP_HSMMC_WRITE(host->base, SYSCTL,
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+ OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
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+
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+ while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
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+ (i++ < limit))
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+ cpu_relax();
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+
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+ if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
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+ dev_err(mmc_dev(host->mmc),
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+ "Timeout waiting on controller reset in %s\n",
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+ __func__);
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+}
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/*
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* MMC controller IRQ handler
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@@ -403,21 +430,17 @@ static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
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(status & CMD_CRC)) {
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if (host->cmd) {
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if (status & CMD_TIMEOUT) {
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- OMAP_HSMMC_WRITE(host->base, SYSCTL,
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- OMAP_HSMMC_READ(host->base,
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- SYSCTL) | SRC);
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- while (OMAP_HSMMC_READ(host->base,
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- SYSCTL) & SRC)
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- ;
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-
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+ mmc_omap_reset_controller_fsm(host, SRC);
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host->cmd->error = -ETIMEDOUT;
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} else {
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host->cmd->error = -EILSEQ;
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}
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end_cmd = 1;
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}
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- if (host->data)
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+ if (host->data) {
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mmc_dma_cleanup(host);
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+ mmc_omap_reset_controller_fsm(host, SRD);
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+ }
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}
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if ((status & DATA_TIMEOUT) ||
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(status & DATA_CRC)) {
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@@ -426,12 +449,7 @@ static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
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mmc_dma_cleanup(host);
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else
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host->data->error = -EILSEQ;
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- OMAP_HSMMC_WRITE(host->base, SYSCTL,
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- OMAP_HSMMC_READ(host->base,
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- SYSCTL) | SRD);
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- while (OMAP_HSMMC_READ(host->base,
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- SYSCTL) & SRD)
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- ;
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+ mmc_omap_reset_controller_fsm(host, SRD);
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end_trans = 1;
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}
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}
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@@ -456,13 +474,20 @@ static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
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}
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/*
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- * Switch MMC operating voltage
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+ * Switch MMC interface voltage ... only relevant for MMC1.
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+ *
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+ * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
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+ * The MMC2 transceiver controls are used instead of DAT4..DAT7.
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+ * Some chips, like eMMC ones, use internal transceivers.
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*/
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static int omap_mmc_switch_opcond(struct mmc_omap_host *host, int vdd)
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{
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u32 reg_val = 0;
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int ret;
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+ if (host->id != OMAP_MMC1_DEVID)
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+ return 0;
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+
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/* Disable the clocks */
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clk_disable(host->fclk);
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clk_disable(host->iclk);
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@@ -485,19 +510,26 @@ static int omap_mmc_switch_opcond(struct mmc_omap_host *host, int vdd)
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OMAP_HSMMC_WRITE(host->base, HCTL,
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OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
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reg_val = OMAP_HSMMC_READ(host->base, HCTL);
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+
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/*
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* If a MMC dual voltage card is detected, the set_ios fn calls
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* this fn with VDD bit set for 1.8V. Upon card removal from the
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* slot, omap_mmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
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*
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- * Only MMC1 supports 3.0V. MMC2 will not function if SDVS30 is
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- * set in HCTL.
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+ * Cope with a bit of slop in the range ... per data sheets:
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+ * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
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+ * but recommended values are 1.71V to 1.89V
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+ * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
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+ * but recommended values are 2.7V to 3.3V
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+ *
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+ * Board setup code shouldn't permit anything very out-of-range.
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+ * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
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+ * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
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*/
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- if (host->id == OMAP_MMC1_DEVID && (((1 << vdd) == MMC_VDD_32_33) ||
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- ((1 << vdd) == MMC_VDD_33_34)))
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- reg_val |= SDVS30;
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- if ((1 << vdd) == MMC_VDD_165_195)
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+ if ((1 << vdd) <= MMC_VDD_23_24)
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reg_val |= SDVS18;
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+ else
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+ reg_val |= SDVS30;
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OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
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@@ -517,16 +549,15 @@ static void mmc_omap_detect(struct work_struct *work)
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{
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struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
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mmc_carddetect_work);
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+ struct omap_mmc_slot_data *slot = &mmc_slot(host);
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+
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+ host->carddetect = slot->card_detect(slot->card_detect_irq);
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sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
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if (host->carddetect) {
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mmc_detect_change(host->mmc, (HZ * 200) / 1000);
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} else {
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- OMAP_HSMMC_WRITE(host->base, SYSCTL,
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- OMAP_HSMMC_READ(host->base, SYSCTL) | SRD);
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- while (OMAP_HSMMC_READ(host->base, SYSCTL) & SRD)
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- ;
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-
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+ mmc_omap_reset_controller_fsm(host, SRD);
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mmc_detect_change(host->mmc, (HZ * 50) / 1000);
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}
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}
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@@ -538,7 +569,6 @@ static irqreturn_t omap_mmc_cd_handler(int irq, void *dev_id)
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{
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struct mmc_omap_host *host = (struct mmc_omap_host *)dev_id;
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- host->carddetect = mmc_slot(host).card_detect(irq);
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schedule_work(&host->mmc_carddetect_work);
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return IRQ_HANDLED;
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@@ -757,10 +787,14 @@ static void omap_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
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case MMC_POWER_OFF:
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mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
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/*
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- * Reset bus voltage to 3V if it got set to 1.8V earlier.
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+ * Reset interface voltage to 3V if it's 1.8V now;
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+ * only relevant on MMC-1, the others always use 1.8V.
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+ *
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* REVISIT: If we are able to detect cards after unplugging
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* a 1.8V card, this code should not be needed.
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*/
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+ if (host->id != OMAP_MMC1_DEVID)
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+ break;
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if (!(OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET)) {
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int vdd = fls(host->mmc->ocr_avail) - 1;
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if (omap_mmc_switch_opcond(host, vdd) != 0)
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@@ -784,7 +818,9 @@ static void omap_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
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}
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if (host->id == OMAP_MMC1_DEVID) {
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- /* Only MMC1 can operate at 3V/1.8V */
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+ /* Only MMC1 can interface at 3V without some flavor
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+ * of external transceiver; but they all handle 1.8V.
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+ */
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if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
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(ios->vdd == DUAL_VOLT_OCR_BIT)) {
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/*
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@@ -1137,7 +1173,9 @@ static int omap_mmc_suspend(struct platform_device *pdev, pm_message_t state)
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" level suspend\n");
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}
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- if (!(OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET)) {
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+ if (host->id == OMAP_MMC1_DEVID
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+ && !(OMAP_HSMMC_READ(host->base, HCTL)
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+ & SDVSDET)) {
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OMAP_HSMMC_WRITE(host->base, HCTL,
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OMAP_HSMMC_READ(host->base, HCTL)
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& SDVSCLR);
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