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@@ -664,79 +664,6 @@ void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select hdmi)
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REG_FLD_MOD(DSS_CONTROL, hdmi, 15, 15); /* VENC_HDMI_SWITCH */
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}
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-static int dss_init(void)
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-{
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- int r;
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- u32 rev;
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- struct resource *dss_mem;
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-
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- dss_mem = platform_get_resource(dss.pdev, IORESOURCE_MEM, 0);
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- if (!dss_mem) {
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- DSSERR("can't get IORESOURCE_MEM DSS\n");
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- r = -EINVAL;
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- goto fail0;
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- }
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- dss.base = ioremap(dss_mem->start, resource_size(dss_mem));
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- if (!dss.base) {
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- DSSERR("can't ioremap DSS\n");
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- r = -ENOMEM;
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- goto fail0;
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- }
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-
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- /* disable LCD and DIGIT output. This seems to fix the synclost
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- * problem that we get, if the bootloader starts the DSS and
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- * the kernel resets it */
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- omap_writel(omap_readl(0x48050440) & ~0x3, 0x48050440);
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-
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-#ifdef CONFIG_OMAP2_DSS_SLEEP_BEFORE_RESET
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- /* We need to wait here a bit, otherwise we sometimes start to
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- * get synclost errors, and after that only power cycle will
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- * restore DSS functionality. I have no idea why this happens.
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- * And we have to wait _before_ resetting the DSS, but after
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- * enabling clocks.
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- *
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- * This bug was at least present on OMAP3430. It's unknown
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- * if it happens on OMAP2 or OMAP3630.
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- */
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- msleep(50);
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-#endif
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-
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- _omap_dss_reset();
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-
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- /* autoidle */
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- REG_FLD_MOD(DSS_SYSCONFIG, 1, 0, 0);
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-
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- /* Select DPLL */
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- REG_FLD_MOD(DSS_CONTROL, 0, 0, 0);
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-
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-#ifdef CONFIG_OMAP2_DSS_VENC
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- REG_FLD_MOD(DSS_CONTROL, 1, 4, 4); /* venc dac demen */
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- REG_FLD_MOD(DSS_CONTROL, 1, 3, 3); /* venc clock 4x enable */
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- REG_FLD_MOD(DSS_CONTROL, 0, 2, 2); /* venc clock mode = normal */
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-#endif
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- dss.dsi_clk_source[0] = OMAP_DSS_CLK_SRC_FCK;
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- dss.dsi_clk_source[1] = OMAP_DSS_CLK_SRC_FCK;
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- dss.dispc_clk_source = OMAP_DSS_CLK_SRC_FCK;
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- dss.lcd_clk_source[0] = OMAP_DSS_CLK_SRC_FCK;
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- dss.lcd_clk_source[1] = OMAP_DSS_CLK_SRC_FCK;
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-
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- dss_save_context();
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-
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- rev = dss_read_reg(DSS_REVISION);
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- printk(KERN_INFO "OMAP DSS rev %d.%d\n",
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- FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
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-
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- return 0;
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-
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-fail0:
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- return r;
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-}
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-
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-static void dss_exit(void)
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-{
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- iounmap(dss.base);
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-}
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-
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/* CONTEXT */
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static int dss_get_ctx_id(void)
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{
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@@ -1094,10 +1021,25 @@ void dss_debug_dump_clocks(struct seq_file *s)
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/* DSS HW IP initialisation */
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static int omap_dsshw_probe(struct platform_device *pdev)
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{
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+ struct resource *dss_mem;
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+ u32 rev;
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int r;
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dss.pdev = pdev;
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+ dss_mem = platform_get_resource(dss.pdev, IORESOURCE_MEM, 0);
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+ if (!dss_mem) {
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+ DSSERR("can't get IORESOURCE_MEM DSS\n");
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+ r = -EINVAL;
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+ goto err_ioremap;
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+ }
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+ dss.base = ioremap(dss_mem->start, resource_size(dss_mem));
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+ if (!dss.base) {
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+ DSSERR("can't ioremap DSS\n");
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+ r = -ENOMEM;
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+ goto err_ioremap;
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+ }
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+
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r = dss_get_clocks();
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if (r)
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goto err_clocks;
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@@ -1107,11 +1049,42 @@ static int omap_dsshw_probe(struct platform_device *pdev)
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dss.ctx_id = dss_get_ctx_id();
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DSSDBG("initial ctx id %u\n", dss.ctx_id);
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- r = dss_init();
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- if (r) {
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- DSSERR("Failed to initialize DSS\n");
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- goto err_dss;
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- }
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+ /* disable LCD and DIGIT output. This seems to fix the synclost
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+ * problem that we get, if the bootloader starts the DSS and
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+ * the kernel resets it */
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+ omap_writel(omap_readl(0x48050440) & ~0x3, 0x48050440);
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+
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+#ifdef CONFIG_OMAP2_DSS_SLEEP_BEFORE_RESET
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+ /* We need to wait here a bit, otherwise we sometimes start to
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+ * get synclost errors, and after that only power cycle will
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+ * restore DSS functionality. I have no idea why this happens.
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+ * And we have to wait _before_ resetting the DSS, but after
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+ * enabling clocks.
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+ *
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+ * This bug was at least present on OMAP3430. It's unknown
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+ * if it happens on OMAP2 or OMAP3630.
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+ */
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+ msleep(50);
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+#endif
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+
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+ _omap_dss_reset();
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+
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+ /* autoidle */
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+ REG_FLD_MOD(DSS_SYSCONFIG, 1, 0, 0);
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+
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+ /* Select DPLL */
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+ REG_FLD_MOD(DSS_CONTROL, 0, 0, 0);
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+
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+#ifdef CONFIG_OMAP2_DSS_VENC
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+ REG_FLD_MOD(DSS_CONTROL, 1, 4, 4); /* venc dac demen */
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+ REG_FLD_MOD(DSS_CONTROL, 1, 3, 3); /* venc clock 4x enable */
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+ REG_FLD_MOD(DSS_CONTROL, 0, 2, 2); /* venc clock mode = normal */
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+#endif
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+ dss.dsi_clk_source[0] = OMAP_DSS_CLK_SRC_FCK;
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+ dss.dsi_clk_source[1] = OMAP_DSS_CLK_SRC_FCK;
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+ dss.dispc_clk_source = OMAP_DSS_CLK_SRC_FCK;
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+ dss.lcd_clk_source[0] = OMAP_DSS_CLK_SRC_FCK;
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+ dss.lcd_clk_source[1] = OMAP_DSS_CLK_SRC_FCK;
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r = dpi_init();
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if (r) {
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@@ -1125,23 +1098,32 @@ static int omap_dsshw_probe(struct platform_device *pdev)
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goto err_sdi;
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}
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+ dss_save_context();
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+
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+ rev = dss_read_reg(DSS_REVISION);
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+ printk(KERN_INFO "OMAP DSS rev %d.%d\n",
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+ FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
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+
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dss_clk_disable_all_no_ctx();
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+
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return 0;
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err_sdi:
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dpi_exit();
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err_dpi:
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- dss_exit();
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-err_dss:
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dss_clk_disable_all_no_ctx();
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dss_put_clocks();
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err_clocks:
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+ iounmap(dss.base);
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+err_ioremap:
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return r;
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}
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static int omap_dsshw_remove(struct platform_device *pdev)
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{
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+ dpi_exit();
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+ sdi_exit();
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- dss_exit();
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+ iounmap(dss.base);
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/*
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* As part of hwmod changes, DSS is not the only controller of dss
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@@ -1152,6 +1134,7 @@ static int omap_dsshw_remove(struct platform_device *pdev)
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WARN_ON(dss.num_clks_enabled > 0);
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dss_put_clocks();
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+
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return 0;
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}
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