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@@ -12,6 +12,17 @@
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*/
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#include <linux/linkage.h>
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+#ifdef CONFIG_CPU_SH4A
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+#define SYNCO() synco
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+
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+#define PREFI(label, reg) \
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+ mov.l label, reg; \
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+ prefi @reg
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+#else
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+#define SYNCO()
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+#define PREFI(label, reg)
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+#endif
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+
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.section .empty_zero_page, "aw"
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ENTRY(empty_zero_page)
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.long 1 /* MOUNT_ROOT_RDONLY */
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@@ -42,6 +53,17 @@ ENTRY(_stext)
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! Initialize global interrupt mask
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mov #0, r0
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ldc r0, r6_bank
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+
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+ /*
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+ * Prefetch if possible to reduce cache miss penalty.
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+ *
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+ * We do this early on for SH-4A as a micro-optimization,
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+ * as later on we will have speculative execution enabled
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+ * and this will become less of an issue.
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+ */
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+ PREFI(5f, r0)
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+ PREFI(6f, r0)
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+
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!
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mov.l 2f, r0
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mov r0, r15 ! Set initial r15 (stack pointer)
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@@ -49,11 +71,7 @@ ENTRY(_stext)
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shll8 r1 ! r1 = 8192
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sub r1, r0 !
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ldc r0, r7_bank ! ... and initial thread_info
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- !
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- ! Additional CPU initialization
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- mov.l 6f, r0
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- jsr @r0
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- nop
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+
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! Clear BSS area
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mov.l 3f, r1
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add #4, r1
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@@ -62,6 +80,14 @@ ENTRY(_stext)
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9: cmp/hs r2, r1
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bf/s 9b ! while (r1 < r2)
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mov.l r0,@-r2
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+
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+ ! Additional CPU initialization
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+ mov.l 6f, r0
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+ jsr @r0
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+ nop
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+
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+ SYNCO() ! Wait for pending instructions..
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+
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! Start kernel
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mov.l 5f, r0
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jmp @r0
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