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@@ -29,7 +29,6 @@
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#include <linux/etherdevice.h>
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#include <linux/etherdevice.h>
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#include <linux/slab.h>
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#include <linux/slab.h>
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#include <linux/sched.h>
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#include <linux/sched.h>
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-#include <net/mac80211.h>
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#include "iwl-agn.h"
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#include "iwl-agn.h"
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#include "iwl-dev.h"
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#include "iwl-dev.h"
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@@ -41,11 +40,13 @@
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/**
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/**
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* iwl_trans_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
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* iwl_trans_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
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*/
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*/
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-void iwl_trans_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
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+void iwl_trans_txq_update_byte_cnt_tbl(struct iwl_trans *trans,
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struct iwl_tx_queue *txq,
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struct iwl_tx_queue *txq,
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u16 byte_cnt)
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u16 byte_cnt)
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{
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{
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- struct iwlagn_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
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+ struct iwlagn_scd_bc_tbl *scd_bc_tbl;
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+ struct iwl_trans_pcie *trans_pcie =
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+ IWL_TRANS_GET_PCIE_TRANS(trans);
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int write_ptr = txq->q.write_ptr;
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int write_ptr = txq->q.write_ptr;
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int txq_id = txq->q.id;
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int txq_id = txq->q.id;
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u8 sec_ctl = 0;
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u8 sec_ctl = 0;
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@@ -53,6 +54,8 @@ void iwl_trans_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
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u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
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u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
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__le16 bc_ent;
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__le16 bc_ent;
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+ scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
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+
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WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
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WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
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sta_id = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id;
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sta_id = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id;
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@@ -82,7 +85,7 @@ void iwl_trans_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
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/**
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/**
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* iwl_txq_update_write_ptr - Send new write index to hardware
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* iwl_txq_update_write_ptr - Send new write index to hardware
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*/
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*/
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-void iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq)
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+void iwl_txq_update_write_ptr(struct iwl_trans *trans, struct iwl_tx_queue *txq)
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{
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{
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u32 reg = 0;
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u32 reg = 0;
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int txq_id = txq->q.id;
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int txq_id = txq->q.id;
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@@ -90,28 +93,28 @@ void iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq)
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if (txq->need_update == 0)
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if (txq->need_update == 0)
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return;
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return;
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- if (priv->cfg->base_params->shadow_reg_enable) {
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+ if (hw_params(trans).shadow_reg_enable) {
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/* shadow register enabled */
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/* shadow register enabled */
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- iwl_write32(priv, HBUS_TARG_WRPTR,
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+ iwl_write32(bus(trans), HBUS_TARG_WRPTR,
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txq->q.write_ptr | (txq_id << 8));
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txq->q.write_ptr | (txq_id << 8));
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} else {
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} else {
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/* if we're trying to save power */
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/* if we're trying to save power */
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- if (test_bit(STATUS_POWER_PMI, &priv->status)) {
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+ if (test_bit(STATUS_POWER_PMI, &trans->shrd->status)) {
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/* wake up nic if it's powered down ...
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/* wake up nic if it's powered down ...
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* uCode will wake up, and interrupt us again, so next
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* uCode will wake up, and interrupt us again, so next
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* time we'll skip this part. */
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* time we'll skip this part. */
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- reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
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+ reg = iwl_read32(bus(trans), CSR_UCODE_DRV_GP1);
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if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
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if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
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- IWL_DEBUG_INFO(priv,
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+ IWL_DEBUG_INFO(trans,
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"Tx queue %d requesting wakeup,"
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"Tx queue %d requesting wakeup,"
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" GP1 = 0x%x\n", txq_id, reg);
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" GP1 = 0x%x\n", txq_id, reg);
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- iwl_set_bit(priv, CSR_GP_CNTRL,
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+ iwl_set_bit(bus(trans), CSR_GP_CNTRL,
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CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
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CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
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return;
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return;
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}
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}
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- iwl_write_direct32(priv, HBUS_TARG_WRPTR,
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+ iwl_write_direct32(bus(trans), HBUS_TARG_WRPTR,
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txq->q.write_ptr | (txq_id << 8));
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txq->q.write_ptr | (txq_id << 8));
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/*
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/*
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@@ -120,7 +123,7 @@ void iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq)
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* trying to tx (during RFKILL, we're not trying to tx).
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* trying to tx (during RFKILL, we're not trying to tx).
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*/
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*/
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} else
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} else
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- iwl_write32(priv, HBUS_TARG_WRPTR,
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+ iwl_write32(bus(trans), HBUS_TARG_WRPTR,
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txq->q.write_ptr | (txq_id << 8));
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txq->q.write_ptr | (txq_id << 8));
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}
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}
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txq->need_update = 0;
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txq->need_update = 0;
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@@ -165,7 +168,7 @@ static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
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return tfd->num_tbs & 0x1f;
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return tfd->num_tbs & 0x1f;
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}
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}
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-static void iwlagn_unmap_tfd(struct iwl_priv *priv, struct iwl_cmd_meta *meta,
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+static void iwlagn_unmap_tfd(struct iwl_trans *trans, struct iwl_cmd_meta *meta,
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struct iwl_tfd *tfd, enum dma_data_direction dma_dir)
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struct iwl_tfd *tfd, enum dma_data_direction dma_dir)
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{
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{
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int i;
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int i;
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@@ -175,56 +178,56 @@ static void iwlagn_unmap_tfd(struct iwl_priv *priv, struct iwl_cmd_meta *meta,
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num_tbs = iwl_tfd_get_num_tbs(tfd);
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num_tbs = iwl_tfd_get_num_tbs(tfd);
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if (num_tbs >= IWL_NUM_OF_TBS) {
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if (num_tbs >= IWL_NUM_OF_TBS) {
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- IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
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+ IWL_ERR(trans, "Too many chunks: %i\n", num_tbs);
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/* @todo issue fatal error, it is quite serious situation */
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/* @todo issue fatal error, it is quite serious situation */
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return;
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return;
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}
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}
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/* Unmap tx_cmd */
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/* Unmap tx_cmd */
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if (num_tbs)
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if (num_tbs)
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- dma_unmap_single(priv->bus->dev,
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+ dma_unmap_single(bus(trans)->dev,
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dma_unmap_addr(meta, mapping),
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dma_unmap_addr(meta, mapping),
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dma_unmap_len(meta, len),
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dma_unmap_len(meta, len),
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DMA_BIDIRECTIONAL);
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DMA_BIDIRECTIONAL);
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/* Unmap chunks, if any. */
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/* Unmap chunks, if any. */
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for (i = 1; i < num_tbs; i++)
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for (i = 1; i < num_tbs; i++)
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- dma_unmap_single(priv->bus->dev, iwl_tfd_tb_get_addr(tfd, i),
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+ dma_unmap_single(bus(trans)->dev, iwl_tfd_tb_get_addr(tfd, i),
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iwl_tfd_tb_get_len(tfd, i), dma_dir);
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iwl_tfd_tb_get_len(tfd, i), dma_dir);
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}
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}
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/**
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/**
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* iwlagn_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
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* iwlagn_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
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- * @priv - driver private data
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+ * @trans - transport private data
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* @txq - tx queue
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* @txq - tx queue
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* @index - the index of the TFD to be freed
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* @index - the index of the TFD to be freed
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*
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*
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* Does NOT advance any TFD circular buffer read/write indexes
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* Does NOT advance any TFD circular buffer read/write indexes
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* Does NOT free the TFD itself (which is within circular buffer)
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* Does NOT free the TFD itself (which is within circular buffer)
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*/
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*/
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-void iwlagn_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq,
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+void iwlagn_txq_free_tfd(struct iwl_trans *trans, struct iwl_tx_queue *txq,
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int index)
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int index)
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{
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{
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struct iwl_tfd *tfd_tmp = txq->tfds;
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struct iwl_tfd *tfd_tmp = txq->tfds;
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- iwlagn_unmap_tfd(priv, &txq->meta[index], &tfd_tmp[index],
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+ iwlagn_unmap_tfd(trans, &txq->meta[index], &tfd_tmp[index],
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DMA_TO_DEVICE);
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DMA_TO_DEVICE);
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/* free SKB */
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/* free SKB */
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- if (txq->txb) {
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+ if (txq->skbs) {
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struct sk_buff *skb;
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struct sk_buff *skb;
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- skb = txq->txb[index].skb;
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+ skb = txq->skbs[index];
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/* can be called from irqs-disabled context */
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/* can be called from irqs-disabled context */
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if (skb) {
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if (skb) {
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dev_kfree_skb_any(skb);
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dev_kfree_skb_any(skb);
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- txq->txb[index].skb = NULL;
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+ txq->skbs[index] = NULL;
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}
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}
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}
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}
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}
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}
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-int iwlagn_txq_attach_buf_to_tfd(struct iwl_priv *priv,
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+int iwlagn_txq_attach_buf_to_tfd(struct iwl_trans *trans,
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struct iwl_tx_queue *txq,
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struct iwl_tx_queue *txq,
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dma_addr_t addr, u16 len,
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dma_addr_t addr, u16 len,
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u8 reset)
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u8 reset)
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@@ -244,7 +247,7 @@ int iwlagn_txq_attach_buf_to_tfd(struct iwl_priv *priv,
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/* Each TFD can point to a maximum 20 Tx buffers */
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/* Each TFD can point to a maximum 20 Tx buffers */
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if (num_tbs >= IWL_NUM_OF_TBS) {
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if (num_tbs >= IWL_NUM_OF_TBS) {
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- IWL_ERR(priv, "Error can not send more than %d chunks\n",
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+ IWL_ERR(trans, "Error can not send more than %d chunks\n",
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IWL_NUM_OF_TBS);
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IWL_NUM_OF_TBS);
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return -EINVAL;
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return -EINVAL;
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}
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}
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@@ -253,7 +256,7 @@ int iwlagn_txq_attach_buf_to_tfd(struct iwl_priv *priv,
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return -EINVAL;
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return -EINVAL;
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if (unlikely(addr & ~IWL_TX_DMA_MASK))
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if (unlikely(addr & ~IWL_TX_DMA_MASK))
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- IWL_ERR(priv, "Unaligned address = %llx\n",
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+ IWL_ERR(trans, "Unaligned address = %llx\n",
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(unsigned long long)addr);
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(unsigned long long)addr);
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iwl_tfd_set_tb(tfd, num_tbs, addr, len);
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iwl_tfd_set_tb(tfd, num_tbs, addr, len);
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@@ -302,8 +305,7 @@ int iwl_queue_space(const struct iwl_queue *q)
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/**
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/**
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* iwl_queue_init - Initialize queue's high/low-water and read/write indexes
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* iwl_queue_init - Initialize queue's high/low-water and read/write indexes
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*/
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*/
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-int iwl_queue_init(struct iwl_priv *priv, struct iwl_queue *q,
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- int count, int slots_num, u32 id)
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+int iwl_queue_init(struct iwl_queue *q, int count, int slots_num, u32 id)
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{
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{
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q->n_bd = count;
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q->n_bd = count;
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q->n_window = slots_num;
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q->n_window = slots_num;
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@@ -332,16 +334,12 @@ int iwl_queue_init(struct iwl_priv *priv, struct iwl_queue *q,
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return 0;
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return 0;
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}
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}
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-/*TODO: this functions should NOT be exported from trans module - export it
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- * until the reclaim flow will be brought to the transport module too.
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- * Add a declaration to make sparse happy */
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-void iwlagn_txq_inval_byte_cnt_tbl(struct iwl_priv *priv,
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- struct iwl_tx_queue *txq);
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-
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-void iwlagn_txq_inval_byte_cnt_tbl(struct iwl_priv *priv,
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+static void iwlagn_txq_inval_byte_cnt_tbl(struct iwl_trans *trans,
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struct iwl_tx_queue *txq)
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struct iwl_tx_queue *txq)
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{
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{
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- struct iwlagn_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
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+ struct iwl_trans_pcie *trans_pcie =
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+ IWL_TRANS_GET_PCIE_TRANS(trans);
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+ struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
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int txq_id = txq->q.id;
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int txq_id = txq->q.id;
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int read_ptr = txq->q.read_ptr;
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int read_ptr = txq->q.read_ptr;
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u8 sta_id = 0;
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u8 sta_id = 0;
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@@ -349,7 +347,7 @@ void iwlagn_txq_inval_byte_cnt_tbl(struct iwl_priv *priv,
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WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
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WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
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- if (txq_id != priv->cmd_queue)
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+ if (txq_id != trans->shrd->cmd_queue)
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sta_id = txq->cmd[read_ptr]->cmd.tx.sta_id;
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sta_id = txq->cmd[read_ptr]->cmd.tx.sta_id;
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bc_ent = cpu_to_le16(1 | (sta_id << 12));
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bc_ent = cpu_to_le16(1 | (sta_id << 12));
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@@ -360,56 +358,61 @@ void iwlagn_txq_inval_byte_cnt_tbl(struct iwl_priv *priv,
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tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
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tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
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}
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}
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-static int iwlagn_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
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+static int iwlagn_tx_queue_set_q2ratid(struct iwl_trans *trans, u16 ra_tid,
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u16 txq_id)
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u16 txq_id)
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{
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{
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u32 tbl_dw_addr;
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u32 tbl_dw_addr;
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u32 tbl_dw;
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u32 tbl_dw;
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u16 scd_q2ratid;
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u16 scd_q2ratid;
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+ struct iwl_trans_pcie *trans_pcie =
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+ IWL_TRANS_GET_PCIE_TRANS(trans);
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+
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scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK;
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scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK;
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- tbl_dw_addr = priv->scd_base_addr +
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+ tbl_dw_addr = trans_pcie->scd_base_addr +
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SCD_TRANS_TBL_OFFSET_QUEUE(txq_id);
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SCD_TRANS_TBL_OFFSET_QUEUE(txq_id);
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- tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
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+ tbl_dw = iwl_read_targ_mem(bus(trans), tbl_dw_addr);
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if (txq_id & 0x1)
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if (txq_id & 0x1)
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tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
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tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
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else
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else
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tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
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tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
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- iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
|
|
|
|
|
|
+ iwl_write_targ_mem(bus(trans), tbl_dw_addr, tbl_dw);
|
|
|
|
|
|
return 0;
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
|
|
-static void iwlagn_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id)
|
|
|
|
|
|
+static void iwlagn_tx_queue_stop_scheduler(struct iwl_trans *trans, u16 txq_id)
|
|
{
|
|
{
|
|
/* Simply stop the queue, but don't change any configuration;
|
|
/* Simply stop the queue, but don't change any configuration;
|
|
* the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
|
|
* the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
|
|
- iwl_write_prph(priv,
|
|
|
|
|
|
+ iwl_write_prph(bus(trans),
|
|
SCD_QUEUE_STATUS_BITS(txq_id),
|
|
SCD_QUEUE_STATUS_BITS(txq_id),
|
|
(0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)|
|
|
(0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)|
|
|
(1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
|
|
(1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
|
|
}
|
|
}
|
|
|
|
|
|
-void iwl_trans_set_wr_ptrs(struct iwl_priv *priv,
|
|
|
|
|
|
+void iwl_trans_set_wr_ptrs(struct iwl_trans *trans,
|
|
int txq_id, u32 index)
|
|
int txq_id, u32 index)
|
|
{
|
|
{
|
|
- iwl_write_direct32(priv, HBUS_TARG_WRPTR,
|
|
|
|
|
|
+ iwl_write_direct32(bus(trans), HBUS_TARG_WRPTR,
|
|
(index & 0xff) | (txq_id << 8));
|
|
(index & 0xff) | (txq_id << 8));
|
|
- iwl_write_prph(priv, SCD_QUEUE_RDPTR(txq_id), index);
|
|
|
|
|
|
+ iwl_write_prph(bus(trans), SCD_QUEUE_RDPTR(txq_id), index);
|
|
}
|
|
}
|
|
|
|
|
|
-void iwl_trans_tx_queue_set_status(struct iwl_priv *priv,
|
|
|
|
|
|
+void iwl_trans_tx_queue_set_status(struct iwl_trans *trans,
|
|
struct iwl_tx_queue *txq,
|
|
struct iwl_tx_queue *txq,
|
|
int tx_fifo_id, int scd_retry)
|
|
int tx_fifo_id, int scd_retry)
|
|
{
|
|
{
|
|
|
|
+ struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
|
int txq_id = txq->q.id;
|
|
int txq_id = txq->q.id;
|
|
- int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0;
|
|
|
|
|
|
+ int active =
|
|
|
|
+ test_bit(txq_id, &trans_pcie->txq_ctx_active_msk) ? 1 : 0;
|
|
|
|
|
|
- iwl_write_prph(priv, SCD_QUEUE_STATUS_BITS(txq_id),
|
|
|
|
|
|
+ iwl_write_prph(bus(trans), SCD_QUEUE_STATUS_BITS(txq_id),
|
|
(active << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
|
|
(active << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
|
|
(tx_fifo_id << SCD_QUEUE_STTS_REG_POS_TXF) |
|
|
(tx_fifo_id << SCD_QUEUE_STTS_REG_POS_TXF) |
|
|
(1 << SCD_QUEUE_STTS_REG_POS_WSL) |
|
|
(1 << SCD_QUEUE_STTS_REG_POS_WSL) |
|
|
@@ -417,55 +420,75 @@ void iwl_trans_tx_queue_set_status(struct iwl_priv *priv,
|
|
|
|
|
|
txq->sched_retry = scd_retry;
|
|
txq->sched_retry = scd_retry;
|
|
|
|
|
|
- IWL_DEBUG_INFO(priv, "%s %s Queue %d on FIFO %d\n",
|
|
|
|
|
|
+ IWL_DEBUG_INFO(trans, "%s %s Queue %d on FIFO %d\n",
|
|
active ? "Activate" : "Deactivate",
|
|
active ? "Activate" : "Deactivate",
|
|
scd_retry ? "BA" : "AC/CMD", txq_id, tx_fifo_id);
|
|
scd_retry ? "BA" : "AC/CMD", txq_id, tx_fifo_id);
|
|
}
|
|
}
|
|
|
|
|
|
-void iwl_trans_txq_agg_setup(struct iwl_priv *priv, int sta_id, int tid,
|
|
|
|
- int frame_limit)
|
|
|
|
|
|
+static inline int get_fifo_from_tid(struct iwl_trans_pcie *trans_pcie,
|
|
|
|
+ u8 ctx, u16 tid)
|
|
|
|
+{
|
|
|
|
+ const u8 *ac_to_fifo = trans_pcie->ac_to_fifo[ctx];
|
|
|
|
+ if (likely(tid < ARRAY_SIZE(tid_to_ac)))
|
|
|
|
+ return ac_to_fifo[tid_to_ac[tid]];
|
|
|
|
+
|
|
|
|
+ /* no support for TIDs 8-15 yet */
|
|
|
|
+ return -EINVAL;
|
|
|
|
+}
|
|
|
|
+
|
|
|
|
+void iwl_trans_pcie_tx_agg_setup(struct iwl_trans *trans,
|
|
|
|
+ enum iwl_rxon_context_id ctx, int sta_id,
|
|
|
|
+ int tid, int frame_limit)
|
|
{
|
|
{
|
|
int tx_fifo, txq_id, ssn_idx;
|
|
int tx_fifo, txq_id, ssn_idx;
|
|
u16 ra_tid;
|
|
u16 ra_tid;
|
|
unsigned long flags;
|
|
unsigned long flags;
|
|
struct iwl_tid_data *tid_data;
|
|
struct iwl_tid_data *tid_data;
|
|
|
|
|
|
|
|
+ struct iwl_trans_pcie *trans_pcie =
|
|
|
|
+ IWL_TRANS_GET_PCIE_TRANS(trans);
|
|
|
|
+
|
|
if (WARN_ON(sta_id == IWL_INVALID_STATION))
|
|
if (WARN_ON(sta_id == IWL_INVALID_STATION))
|
|
return;
|
|
return;
|
|
- if (WARN_ON(tid >= MAX_TID_COUNT))
|
|
|
|
|
|
+ if (WARN_ON(tid >= IWL_MAX_TID_COUNT))
|
|
return;
|
|
return;
|
|
|
|
|
|
- spin_lock_irqsave(&priv->sta_lock, flags);
|
|
|
|
- tid_data = &priv->stations[sta_id].tid[tid];
|
|
|
|
|
|
+ tx_fifo = get_fifo_from_tid(trans_pcie, ctx, tid);
|
|
|
|
+ if (WARN_ON(tx_fifo < 0)) {
|
|
|
|
+ IWL_ERR(trans, "txq_agg_setup, bad fifo: %d\n", tx_fifo);
|
|
|
|
+ return;
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
+ spin_lock_irqsave(&trans->shrd->sta_lock, flags);
|
|
|
|
+ tid_data = &trans->shrd->tid_data[sta_id][tid];
|
|
ssn_idx = SEQ_TO_SN(tid_data->seq_number);
|
|
ssn_idx = SEQ_TO_SN(tid_data->seq_number);
|
|
txq_id = tid_data->agg.txq_id;
|
|
txq_id = tid_data->agg.txq_id;
|
|
- tx_fifo = tid_data->agg.tx_fifo;
|
|
|
|
- spin_unlock_irqrestore(&priv->sta_lock, flags);
|
|
|
|
|
|
+ spin_unlock_irqrestore(&trans->shrd->sta_lock, flags);
|
|
|
|
|
|
ra_tid = BUILD_RAxTID(sta_id, tid);
|
|
ra_tid = BUILD_RAxTID(sta_id, tid);
|
|
|
|
|
|
- spin_lock_irqsave(&priv->lock, flags);
|
|
|
|
|
|
+ spin_lock_irqsave(&trans->shrd->lock, flags);
|
|
|
|
|
|
/* Stop this Tx queue before configuring it */
|
|
/* Stop this Tx queue before configuring it */
|
|
- iwlagn_tx_queue_stop_scheduler(priv, txq_id);
|
|
|
|
|
|
+ iwlagn_tx_queue_stop_scheduler(trans, txq_id);
|
|
|
|
|
|
/* Map receiver-address / traffic-ID to this queue */
|
|
/* Map receiver-address / traffic-ID to this queue */
|
|
- iwlagn_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
|
|
|
|
|
|
+ iwlagn_tx_queue_set_q2ratid(trans, ra_tid, txq_id);
|
|
|
|
|
|
/* Set this queue as a chain-building queue */
|
|
/* Set this queue as a chain-building queue */
|
|
- iwl_set_bits_prph(priv, SCD_QUEUECHAIN_SEL, (1<<txq_id));
|
|
|
|
|
|
+ iwl_set_bits_prph(bus(trans), SCD_QUEUECHAIN_SEL, (1<<txq_id));
|
|
|
|
|
|
/* enable aggregations for the queue */
|
|
/* enable aggregations for the queue */
|
|
- iwl_set_bits_prph(priv, SCD_AGGR_SEL, (1<<txq_id));
|
|
|
|
|
|
+ iwl_set_bits_prph(bus(trans), SCD_AGGR_SEL, (1<<txq_id));
|
|
|
|
|
|
/* Place first TFD at index corresponding to start sequence number.
|
|
/* Place first TFD at index corresponding to start sequence number.
|
|
* Assumes that ssn_idx is valid (!= 0xFFF) */
|
|
* Assumes that ssn_idx is valid (!= 0xFFF) */
|
|
- priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
|
|
|
|
- priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
|
|
|
|
- iwl_trans_set_wr_ptrs(priv, txq_id, ssn_idx);
|
|
|
|
|
|
+ trans_pcie->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
|
|
|
|
+ trans_pcie->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
|
|
|
|
+ iwl_trans_set_wr_ptrs(trans, txq_id, ssn_idx);
|
|
|
|
|
|
/* Set up Tx window size and frame limit for this queue */
|
|
/* Set up Tx window size and frame limit for this queue */
|
|
- iwl_write_targ_mem(priv, priv->scd_base_addr +
|
|
|
|
|
|
+ iwl_write_targ_mem(bus(trans), trans_pcie->scd_base_addr +
|
|
SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
|
|
SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
|
|
sizeof(u32),
|
|
sizeof(u32),
|
|
((frame_limit <<
|
|
((frame_limit <<
|
|
@@ -475,40 +498,159 @@ void iwl_trans_txq_agg_setup(struct iwl_priv *priv, int sta_id, int tid,
|
|
SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
|
|
SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
|
|
SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
|
|
SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
|
|
|
|
|
|
- iwl_set_bits_prph(priv, SCD_INTERRUPT_MASK, (1 << txq_id));
|
|
|
|
|
|
+ iwl_set_bits_prph(bus(trans), SCD_INTERRUPT_MASK, (1 << txq_id));
|
|
|
|
|
|
/* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
|
|
/* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
|
|
- iwl_trans_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
|
|
|
|
|
|
+ iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[txq_id],
|
|
|
|
+ tx_fifo, 1);
|
|
|
|
+
|
|
|
|
+ trans_pcie->txq[txq_id].sta_id = sta_id;
|
|
|
|
+ trans_pcie->txq[txq_id].tid = tid;
|
|
|
|
+
|
|
|
|
+ spin_unlock_irqrestore(&trans->shrd->lock, flags);
|
|
|
|
+}
|
|
|
|
+
|
|
|
|
+/*
|
|
|
|
+ * Find first available (lowest unused) Tx Queue, mark it "active".
|
|
|
|
+ * Called only when finding queue for aggregation.
|
|
|
|
+ * Should never return anything < 7, because they should already
|
|
|
|
+ * be in use as EDCA AC (0-3), Command (4), reserved (5, 6)
|
|
|
|
+ */
|
|
|
|
+static int iwlagn_txq_ctx_activate_free(struct iwl_trans *trans)
|
|
|
|
+{
|
|
|
|
+ struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
|
|
|
+ int txq_id;
|
|
|
|
+
|
|
|
|
+ for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++)
|
|
|
|
+ if (!test_and_set_bit(txq_id,
|
|
|
|
+ &trans_pcie->txq_ctx_active_msk))
|
|
|
|
+ return txq_id;
|
|
|
|
+ return -1;
|
|
|
|
+}
|
|
|
|
+
|
|
|
|
+int iwl_trans_pcie_tx_agg_alloc(struct iwl_trans *trans,
|
|
|
|
+ enum iwl_rxon_context_id ctx, int sta_id,
|
|
|
|
+ int tid, u16 *ssn)
|
|
|
|
+{
|
|
|
|
+ struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
|
|
|
+ struct iwl_tid_data *tid_data;
|
|
|
|
+ unsigned long flags;
|
|
|
|
+ u16 txq_id;
|
|
|
|
+ struct iwl_priv *priv = priv(trans);
|
|
|
|
+
|
|
|
|
+ txq_id = iwlagn_txq_ctx_activate_free(trans);
|
|
|
|
+ if (txq_id == -1) {
|
|
|
|
+ IWL_ERR(trans, "No free aggregation queue available\n");
|
|
|
|
+ return -ENXIO;
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
+ spin_lock_irqsave(&trans->shrd->sta_lock, flags);
|
|
|
|
+ tid_data = &trans->shrd->tid_data[sta_id][tid];
|
|
|
|
+ *ssn = SEQ_TO_SN(tid_data->seq_number);
|
|
|
|
+ tid_data->agg.txq_id = txq_id;
|
|
|
|
+ iwl_set_swq_id(&trans_pcie->txq[txq_id], get_ac_from_tid(tid), txq_id);
|
|
|
|
+
|
|
|
|
+ tid_data = &trans->shrd->tid_data[sta_id][tid];
|
|
|
|
+ if (tid_data->tfds_in_queue == 0) {
|
|
|
|
+ IWL_DEBUG_HT(trans, "HW queue is empty\n");
|
|
|
|
+ tid_data->agg.state = IWL_AGG_ON;
|
|
|
|
+ iwl_start_tx_ba_trans_ready(priv(trans), ctx, sta_id, tid);
|
|
|
|
+ } else {
|
|
|
|
+ IWL_DEBUG_HT(trans, "HW queue is NOT empty: %d packets in HW"
|
|
|
|
+ "queue\n", tid_data->tfds_in_queue);
|
|
|
|
+ tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA;
|
|
|
|
+ }
|
|
|
|
+ spin_unlock_irqrestore(&priv->shrd->sta_lock, flags);
|
|
|
|
+
|
|
|
|
+ return 0;
|
|
|
|
+}
|
|
|
|
+
|
|
|
|
+void iwl_trans_pcie_txq_agg_disable(struct iwl_trans *trans, int txq_id)
|
|
|
|
+{
|
|
|
|
+ struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
|
|
|
+ iwlagn_tx_queue_stop_scheduler(trans, txq_id);
|
|
|
|
+
|
|
|
|
+ iwl_clear_bits_prph(bus(trans), SCD_AGGR_SEL, (1 << txq_id));
|
|
|
|
+
|
|
|
|
+ trans_pcie->txq[txq_id].q.read_ptr = 0;
|
|
|
|
+ trans_pcie->txq[txq_id].q.write_ptr = 0;
|
|
|
|
+ /* supposes that ssn_idx is valid (!= 0xFFF) */
|
|
|
|
+ iwl_trans_set_wr_ptrs(trans, txq_id, 0);
|
|
|
|
|
|
- spin_unlock_irqrestore(&priv->lock, flags);
|
|
|
|
|
|
+ iwl_clear_bits_prph(bus(trans), SCD_INTERRUPT_MASK, (1 << txq_id));
|
|
|
|
+ iwl_txq_ctx_deactivate(trans_pcie, txq_id);
|
|
|
|
+ iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[txq_id], 0, 0);
|
|
}
|
|
}
|
|
|
|
|
|
-int iwl_trans_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
|
|
|
|
- u16 ssn_idx, u8 tx_fifo)
|
|
|
|
|
|
+int iwl_trans_pcie_tx_agg_disable(struct iwl_trans *trans,
|
|
|
|
+ enum iwl_rxon_context_id ctx, int sta_id,
|
|
|
|
+ int tid)
|
|
{
|
|
{
|
|
|
|
+ struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
|
|
|
+ unsigned long flags;
|
|
|
|
+ int read_ptr, write_ptr;
|
|
|
|
+ struct iwl_tid_data *tid_data;
|
|
|
|
+ int txq_id;
|
|
|
|
+
|
|
|
|
+ spin_lock_irqsave(&trans->shrd->sta_lock, flags);
|
|
|
|
+
|
|
|
|
+ tid_data = &trans->shrd->tid_data[sta_id][tid];
|
|
|
|
+ txq_id = tid_data->agg.txq_id;
|
|
|
|
+
|
|
if ((IWLAGN_FIRST_AMPDU_QUEUE > txq_id) ||
|
|
if ((IWLAGN_FIRST_AMPDU_QUEUE > txq_id) ||
|
|
(IWLAGN_FIRST_AMPDU_QUEUE +
|
|
(IWLAGN_FIRST_AMPDU_QUEUE +
|
|
- priv->cfg->base_params->num_of_ampdu_queues <= txq_id)) {
|
|
|
|
- IWL_ERR(priv,
|
|
|
|
|
|
+ hw_params(trans).num_ampdu_queues <= txq_id)) {
|
|
|
|
+ IWL_ERR(trans,
|
|
"queue number out of range: %d, must be %d to %d\n",
|
|
"queue number out of range: %d, must be %d to %d\n",
|
|
txq_id, IWLAGN_FIRST_AMPDU_QUEUE,
|
|
txq_id, IWLAGN_FIRST_AMPDU_QUEUE,
|
|
IWLAGN_FIRST_AMPDU_QUEUE +
|
|
IWLAGN_FIRST_AMPDU_QUEUE +
|
|
- priv->cfg->base_params->num_of_ampdu_queues - 1);
|
|
|
|
|
|
+ hw_params(trans).num_ampdu_queues - 1);
|
|
|
|
+ spin_unlock_irqrestore(&trans->shrd->sta_lock, flags);
|
|
return -EINVAL;
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
|
|
|
|
- iwlagn_tx_queue_stop_scheduler(priv, txq_id);
|
|
|
|
|
|
+ switch (trans->shrd->tid_data[sta_id][tid].agg.state) {
|
|
|
|
+ case IWL_EMPTYING_HW_QUEUE_ADDBA:
|
|
|
|
+ /*
|
|
|
|
+ * This can happen if the peer stops aggregation
|
|
|
|
+ * again before we've had a chance to drain the
|
|
|
|
+ * queue we selected previously, i.e. before the
|
|
|
|
+ * session was really started completely.
|
|
|
|
+ */
|
|
|
|
+ IWL_DEBUG_HT(trans, "AGG stop before setup done\n");
|
|
|
|
+ goto turn_off;
|
|
|
|
+ case IWL_AGG_ON:
|
|
|
|
+ break;
|
|
|
|
+ default:
|
|
|
|
+ IWL_WARN(trans, "Stopping AGG while state not ON"
|
|
|
|
+ "or starting\n");
|
|
|
|
+ }
|
|
|
|
|
|
- iwl_clear_bits_prph(priv, SCD_AGGR_SEL, (1 << txq_id));
|
|
|
|
|
|
+ write_ptr = trans_pcie->txq[txq_id].q.write_ptr;
|
|
|
|
+ read_ptr = trans_pcie->txq[txq_id].q.read_ptr;
|
|
|
|
|
|
- priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
|
|
|
|
- priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
|
|
|
|
- /* supposes that ssn_idx is valid (!= 0xFFF) */
|
|
|
|
- iwl_trans_set_wr_ptrs(priv, txq_id, ssn_idx);
|
|
|
|
|
|
+ /* The queue is not empty */
|
|
|
|
+ if (write_ptr != read_ptr) {
|
|
|
|
+ IWL_DEBUG_HT(trans, "Stopping a non empty AGG HW QUEUE\n");
|
|
|
|
+ trans->shrd->tid_data[sta_id][tid].agg.state =
|
|
|
|
+ IWL_EMPTYING_HW_QUEUE_DELBA;
|
|
|
|
+ spin_unlock_irqrestore(&trans->shrd->sta_lock, flags);
|
|
|
|
+ return 0;
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
+ IWL_DEBUG_HT(trans, "HW queue is empty\n");
|
|
|
|
+turn_off:
|
|
|
|
+ trans->shrd->tid_data[sta_id][tid].agg.state = IWL_AGG_OFF;
|
|
|
|
+
|
|
|
|
+ /* do not restore/save irqs */
|
|
|
|
+ spin_unlock(&trans->shrd->sta_lock);
|
|
|
|
+ spin_lock(&trans->shrd->lock);
|
|
|
|
+
|
|
|
|
+ iwl_trans_pcie_txq_agg_disable(trans, txq_id);
|
|
|
|
+
|
|
|
|
+ spin_unlock_irqrestore(&trans->shrd->lock, flags);
|
|
|
|
|
|
- iwl_clear_bits_prph(priv, SCD_INTERRUPT_MASK, (1 << txq_id));
|
|
|
|
- iwl_txq_ctx_deactivate(priv, txq_id);
|
|
|
|
- iwl_trans_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
|
|
|
|
|
|
+ iwl_stop_tx_ba_trans_ready(priv(trans), ctx, sta_id, tid);
|
|
|
|
|
|
return 0;
|
|
return 0;
|
|
}
|
|
}
|
|
@@ -524,9 +666,10 @@ int iwl_trans_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
|
|
* failed. On success, it turns the index (> 0) of command in the
|
|
* failed. On success, it turns the index (> 0) of command in the
|
|
* command queue.
|
|
* command queue.
|
|
*/
|
|
*/
|
|
-static int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
|
|
|
|
|
|
+static int iwl_enqueue_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
|
|
{
|
|
{
|
|
- struct iwl_tx_queue *txq = &priv->txq[priv->cmd_queue];
|
|
|
|
|
|
+ struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
|
|
|
+ struct iwl_tx_queue *txq = &trans_pcie->txq[trans->shrd->cmd_queue];
|
|
struct iwl_queue *q = &txq->q;
|
|
struct iwl_queue *q = &txq->q;
|
|
struct iwl_device_cmd *out_cmd;
|
|
struct iwl_device_cmd *out_cmd;
|
|
struct iwl_cmd_meta *out_meta;
|
|
struct iwl_cmd_meta *out_meta;
|
|
@@ -544,14 +687,14 @@ static int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
|
|
int trace_idx;
|
|
int trace_idx;
|
|
#endif
|
|
#endif
|
|
|
|
|
|
- if (test_bit(STATUS_FW_ERROR, &priv->status)) {
|
|
|
|
- IWL_WARN(priv, "fw recovery, no hcmd send\n");
|
|
|
|
|
|
+ if (test_bit(STATUS_FW_ERROR, &trans->shrd->status)) {
|
|
|
|
+ IWL_WARN(trans, "fw recovery, no hcmd send\n");
|
|
return -EIO;
|
|
return -EIO;
|
|
}
|
|
}
|
|
|
|
|
|
- if ((priv->ucode_owner == IWL_OWNERSHIP_TM) &&
|
|
|
|
|
|
+ if ((trans->shrd->ucode_owner == IWL_OWNERSHIP_TM) &&
|
|
!(cmd->flags & CMD_ON_DEMAND)) {
|
|
!(cmd->flags & CMD_ON_DEMAND)) {
|
|
- IWL_DEBUG_HC(priv, "tm own the uCode, no regular hcmd send\n");
|
|
|
|
|
|
+ IWL_DEBUG_HC(trans, "tm own the uCode, no regular hcmd send\n");
|
|
return -EIO;
|
|
return -EIO;
|
|
}
|
|
}
|
|
|
|
|
|
@@ -584,22 +727,22 @@ static int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
|
|
if (WARN_ON(copy_size > TFD_MAX_PAYLOAD_SIZE))
|
|
if (WARN_ON(copy_size > TFD_MAX_PAYLOAD_SIZE))
|
|
return -EINVAL;
|
|
return -EINVAL;
|
|
|
|
|
|
- if (iwl_is_rfkill(priv) || iwl_is_ctkill(priv)) {
|
|
|
|
- IWL_WARN(priv, "Not sending command - %s KILL\n",
|
|
|
|
- iwl_is_rfkill(priv) ? "RF" : "CT");
|
|
|
|
|
|
+ if (iwl_is_rfkill(trans->shrd) || iwl_is_ctkill(trans->shrd)) {
|
|
|
|
+ IWL_WARN(trans, "Not sending command - %s KILL\n",
|
|
|
|
+ iwl_is_rfkill(trans->shrd) ? "RF" : "CT");
|
|
return -EIO;
|
|
return -EIO;
|
|
}
|
|
}
|
|
|
|
|
|
- spin_lock_irqsave(&priv->hcmd_lock, flags);
|
|
|
|
|
|
+ spin_lock_irqsave(&trans->hcmd_lock, flags);
|
|
|
|
|
|
if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
|
|
if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
|
|
- spin_unlock_irqrestore(&priv->hcmd_lock, flags);
|
|
|
|
|
|
+ spin_unlock_irqrestore(&trans->hcmd_lock, flags);
|
|
|
|
|
|
- IWL_ERR(priv, "No space in command queue\n");
|
|
|
|
- is_ct_kill = iwl_check_for_ct_kill(priv);
|
|
|
|
|
|
+ IWL_ERR(trans, "No space in command queue\n");
|
|
|
|
+ is_ct_kill = iwl_check_for_ct_kill(priv(trans));
|
|
if (!is_ct_kill) {
|
|
if (!is_ct_kill) {
|
|
- IWL_ERR(priv, "Restarting adapter due to queue full\n");
|
|
|
|
- iwlagn_fw_error(priv, false);
|
|
|
|
|
|
+ IWL_ERR(trans, "Restarting adapter queue is full\n");
|
|
|
|
+ iwlagn_fw_error(priv(trans), false);
|
|
}
|
|
}
|
|
return -ENOSPC;
|
|
return -ENOSPC;
|
|
}
|
|
}
|
|
@@ -618,8 +761,9 @@ static int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
|
|
|
|
|
|
out_cmd->hdr.cmd = cmd->id;
|
|
out_cmd->hdr.cmd = cmd->id;
|
|
out_cmd->hdr.flags = 0;
|
|
out_cmd->hdr.flags = 0;
|
|
- out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(priv->cmd_queue) |
|
|
|
|
- INDEX_TO_SEQ(q->write_ptr));
|
|
|
|
|
|
+ out_cmd->hdr.sequence =
|
|
|
|
+ cpu_to_le16(QUEUE_TO_SEQ(trans->shrd->cmd_queue) |
|
|
|
|
+ INDEX_TO_SEQ(q->write_ptr));
|
|
|
|
|
|
/* and copy the data that needs to be copied */
|
|
/* and copy the data that needs to be copied */
|
|
|
|
|
|
@@ -633,16 +777,16 @@ static int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
|
|
cmd_dest += cmd->len[i];
|
|
cmd_dest += cmd->len[i];
|
|
}
|
|
}
|
|
|
|
|
|
- IWL_DEBUG_HC(priv, "Sending command %s (#%x), seq: 0x%04X, "
|
|
|
|
|
|
+ IWL_DEBUG_HC(trans, "Sending command %s (#%x), seq: 0x%04X, "
|
|
"%d bytes at %d[%d]:%d\n",
|
|
"%d bytes at %d[%d]:%d\n",
|
|
get_cmd_string(out_cmd->hdr.cmd),
|
|
get_cmd_string(out_cmd->hdr.cmd),
|
|
out_cmd->hdr.cmd,
|
|
out_cmd->hdr.cmd,
|
|
le16_to_cpu(out_cmd->hdr.sequence), cmd_size,
|
|
le16_to_cpu(out_cmd->hdr.sequence), cmd_size,
|
|
- q->write_ptr, idx, priv->cmd_queue);
|
|
|
|
|
|
+ q->write_ptr, idx, trans->shrd->cmd_queue);
|
|
|
|
|
|
- phys_addr = dma_map_single(priv->bus->dev, &out_cmd->hdr, copy_size,
|
|
|
|
|
|
+ phys_addr = dma_map_single(bus(trans)->dev, &out_cmd->hdr, copy_size,
|
|
DMA_BIDIRECTIONAL);
|
|
DMA_BIDIRECTIONAL);
|
|
- if (unlikely(dma_mapping_error(priv->bus->dev, phys_addr))) {
|
|
|
|
|
|
+ if (unlikely(dma_mapping_error(bus(trans)->dev, phys_addr))) {
|
|
idx = -ENOMEM;
|
|
idx = -ENOMEM;
|
|
goto out;
|
|
goto out;
|
|
}
|
|
}
|
|
@@ -650,7 +794,8 @@ static int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
|
|
dma_unmap_addr_set(out_meta, mapping, phys_addr);
|
|
dma_unmap_addr_set(out_meta, mapping, phys_addr);
|
|
dma_unmap_len_set(out_meta, len, copy_size);
|
|
dma_unmap_len_set(out_meta, len, copy_size);
|
|
|
|
|
|
- iwlagn_txq_attach_buf_to_tfd(priv, txq, phys_addr, copy_size, 1);
|
|
|
|
|
|
+ iwlagn_txq_attach_buf_to_tfd(trans, txq,
|
|
|
|
+ phys_addr, copy_size, 1);
|
|
#ifdef CONFIG_IWLWIFI_DEVICE_TRACING
|
|
#ifdef CONFIG_IWLWIFI_DEVICE_TRACING
|
|
trace_bufs[0] = &out_cmd->hdr;
|
|
trace_bufs[0] = &out_cmd->hdr;
|
|
trace_lens[0] = copy_size;
|
|
trace_lens[0] = copy_size;
|
|
@@ -662,17 +807,18 @@ static int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
|
|
continue;
|
|
continue;
|
|
if (!(cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY))
|
|
if (!(cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY))
|
|
continue;
|
|
continue;
|
|
- phys_addr = dma_map_single(priv->bus->dev, (void *)cmd->data[i],
|
|
|
|
|
|
+ phys_addr = dma_map_single(bus(trans)->dev,
|
|
|
|
+ (void *)cmd->data[i],
|
|
cmd->len[i], DMA_BIDIRECTIONAL);
|
|
cmd->len[i], DMA_BIDIRECTIONAL);
|
|
- if (dma_mapping_error(priv->bus->dev, phys_addr)) {
|
|
|
|
- iwlagn_unmap_tfd(priv, out_meta,
|
|
|
|
|
|
+ if (dma_mapping_error(bus(trans)->dev, phys_addr)) {
|
|
|
|
+ iwlagn_unmap_tfd(trans, out_meta,
|
|
&txq->tfds[q->write_ptr],
|
|
&txq->tfds[q->write_ptr],
|
|
DMA_BIDIRECTIONAL);
|
|
DMA_BIDIRECTIONAL);
|
|
idx = -ENOMEM;
|
|
idx = -ENOMEM;
|
|
goto out;
|
|
goto out;
|
|
}
|
|
}
|
|
|
|
|
|
- iwlagn_txq_attach_buf_to_tfd(priv, txq, phys_addr,
|
|
|
|
|
|
+ iwlagn_txq_attach_buf_to_tfd(trans, txq, phys_addr,
|
|
cmd->len[i], 0);
|
|
cmd->len[i], 0);
|
|
#ifdef CONFIG_IWLWIFI_DEVICE_TRACING
|
|
#ifdef CONFIG_IWLWIFI_DEVICE_TRACING
|
|
trace_bufs[trace_idx] = cmd->data[i];
|
|
trace_bufs[trace_idx] = cmd->data[i];
|
|
@@ -688,7 +834,7 @@ static int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
|
|
/* check that tracing gets all possible blocks */
|
|
/* check that tracing gets all possible blocks */
|
|
BUILD_BUG_ON(IWL_MAX_CMD_TFDS + 1 != 3);
|
|
BUILD_BUG_ON(IWL_MAX_CMD_TFDS + 1 != 3);
|
|
#ifdef CONFIG_IWLWIFI_DEVICE_TRACING
|
|
#ifdef CONFIG_IWLWIFI_DEVICE_TRACING
|
|
- trace_iwlwifi_dev_hcmd(priv, cmd->flags,
|
|
|
|
|
|
+ trace_iwlwifi_dev_hcmd(priv(trans), cmd->flags,
|
|
trace_bufs[0], trace_lens[0],
|
|
trace_bufs[0], trace_lens[0],
|
|
trace_bufs[1], trace_lens[1],
|
|
trace_bufs[1], trace_lens[1],
|
|
trace_bufs[2], trace_lens[2]);
|
|
trace_bufs[2], trace_lens[2]);
|
|
@@ -696,10 +842,10 @@ static int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
|
|
|
|
|
|
/* Increment and update queue's write index */
|
|
/* Increment and update queue's write index */
|
|
q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
|
|
q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
|
|
- iwl_txq_update_write_ptr(priv, txq);
|
|
|
|
|
|
+ iwl_txq_update_write_ptr(trans, txq);
|
|
|
|
|
|
out:
|
|
out:
|
|
- spin_unlock_irqrestore(&priv->hcmd_lock, flags);
|
|
|
|
|
|
+ spin_unlock_irqrestore(&trans->hcmd_lock, flags);
|
|
return idx;
|
|
return idx;
|
|
}
|
|
}
|
|
|
|
|
|
@@ -712,7 +858,9 @@ static int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
|
|
*/
|
|
*/
|
|
static void iwl_hcmd_queue_reclaim(struct iwl_priv *priv, int txq_id, int idx)
|
|
static void iwl_hcmd_queue_reclaim(struct iwl_priv *priv, int txq_id, int idx)
|
|
{
|
|
{
|
|
- struct iwl_tx_queue *txq = &priv->txq[txq_id];
|
|
|
|
|
|
+ struct iwl_trans_pcie *trans_pcie =
|
|
|
|
+ IWL_TRANS_GET_PCIE_TRANS(trans(priv));
|
|
|
|
+ struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
|
|
struct iwl_queue *q = &txq->q;
|
|
struct iwl_queue *q = &txq->q;
|
|
int nfreed = 0;
|
|
int nfreed = 0;
|
|
|
|
|
|
@@ -752,17 +900,19 @@ void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
|
|
int cmd_index;
|
|
int cmd_index;
|
|
struct iwl_device_cmd *cmd;
|
|
struct iwl_device_cmd *cmd;
|
|
struct iwl_cmd_meta *meta;
|
|
struct iwl_cmd_meta *meta;
|
|
- struct iwl_tx_queue *txq = &priv->txq[priv->cmd_queue];
|
|
|
|
|
|
+ struct iwl_trans *trans = trans(priv);
|
|
|
|
+ struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
|
|
|
+ struct iwl_tx_queue *txq = &trans_pcie->txq[trans->shrd->cmd_queue];
|
|
unsigned long flags;
|
|
unsigned long flags;
|
|
|
|
|
|
/* If a Tx command is being handled and it isn't in the actual
|
|
/* If a Tx command is being handled and it isn't in the actual
|
|
* command queue then there a command routing bug has been introduced
|
|
* command queue then there a command routing bug has been introduced
|
|
* in the queue management code. */
|
|
* in the queue management code. */
|
|
- if (WARN(txq_id != priv->cmd_queue,
|
|
|
|
|
|
+ if (WARN(txq_id != trans->shrd->cmd_queue,
|
|
"wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
|
|
"wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
|
|
- txq_id, priv->cmd_queue, sequence,
|
|
|
|
- priv->txq[priv->cmd_queue].q.read_ptr,
|
|
|
|
- priv->txq[priv->cmd_queue].q.write_ptr)) {
|
|
|
|
|
|
+ txq_id, trans->shrd->cmd_queue, sequence,
|
|
|
|
+ trans_pcie->txq[trans->shrd->cmd_queue].q.read_ptr,
|
|
|
|
+ trans_pcie->txq[trans->shrd->cmd_queue].q.write_ptr)) {
|
|
iwl_print_hex_error(priv, pkt, 32);
|
|
iwl_print_hex_error(priv, pkt, 32);
|
|
return;
|
|
return;
|
|
}
|
|
}
|
|
@@ -771,7 +921,8 @@ void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
|
|
cmd = txq->cmd[cmd_index];
|
|
cmd = txq->cmd[cmd_index];
|
|
meta = &txq->meta[cmd_index];
|
|
meta = &txq->meta[cmd_index];
|
|
|
|
|
|
- iwlagn_unmap_tfd(priv, meta, &txq->tfds[index], DMA_BIDIRECTIONAL);
|
|
|
|
|
|
+ iwlagn_unmap_tfd(trans, meta, &txq->tfds[index],
|
|
|
|
+ DMA_BIDIRECTIONAL);
|
|
|
|
|
|
/* Input error checking is done when commands are added to queue. */
|
|
/* Input error checking is done when commands are added to queue. */
|
|
if (meta->flags & CMD_WANT_SKB) {
|
|
if (meta->flags & CMD_WANT_SKB) {
|
|
@@ -780,20 +931,20 @@ void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
|
|
} else if (meta->callback)
|
|
} else if (meta->callback)
|
|
meta->callback(priv, cmd, pkt);
|
|
meta->callback(priv, cmd, pkt);
|
|
|
|
|
|
- spin_lock_irqsave(&priv->hcmd_lock, flags);
|
|
|
|
|
|
+ spin_lock_irqsave(&trans->hcmd_lock, flags);
|
|
|
|
|
|
iwl_hcmd_queue_reclaim(priv, txq_id, index);
|
|
iwl_hcmd_queue_reclaim(priv, txq_id, index);
|
|
|
|
|
|
if (!(meta->flags & CMD_ASYNC)) {
|
|
if (!(meta->flags & CMD_ASYNC)) {
|
|
- clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
|
|
|
|
- IWL_DEBUG_INFO(priv, "Clearing HCMD_ACTIVE for command %s\n",
|
|
|
|
|
|
+ clear_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status);
|
|
|
|
+ IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
|
|
get_cmd_string(cmd->hdr.cmd));
|
|
get_cmd_string(cmd->hdr.cmd));
|
|
wake_up_interruptible(&priv->wait_command_queue);
|
|
wake_up_interruptible(&priv->wait_command_queue);
|
|
}
|
|
}
|
|
|
|
|
|
meta->flags = 0;
|
|
meta->flags = 0;
|
|
|
|
|
|
- spin_unlock_irqrestore(&priv->hcmd_lock, flags);
|
|
|
|
|
|
+ spin_unlock_irqrestore(&trans->hcmd_lock, flags);
|
|
}
|
|
}
|
|
|
|
|
|
const char *get_cmd_string(u8 cmd)
|
|
const char *get_cmd_string(u8 cmd)
|
|
@@ -904,7 +1055,7 @@ static void iwl_generic_cmd_callback(struct iwl_priv *priv,
|
|
#endif
|
|
#endif
|
|
}
|
|
}
|
|
|
|
|
|
-static int iwl_send_cmd_async(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
|
|
|
|
|
|
+static int iwl_send_cmd_async(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
|
|
{
|
|
{
|
|
int ret;
|
|
int ret;
|
|
|
|
|
|
@@ -916,77 +1067,78 @@ static int iwl_send_cmd_async(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
|
|
if (!cmd->callback)
|
|
if (!cmd->callback)
|
|
cmd->callback = iwl_generic_cmd_callback;
|
|
cmd->callback = iwl_generic_cmd_callback;
|
|
|
|
|
|
- if (test_bit(STATUS_EXIT_PENDING, &priv->status))
|
|
|
|
|
|
+ if (test_bit(STATUS_EXIT_PENDING, &trans->shrd->status))
|
|
return -EBUSY;
|
|
return -EBUSY;
|
|
|
|
|
|
- ret = iwl_enqueue_hcmd(priv, cmd);
|
|
|
|
|
|
+ ret = iwl_enqueue_hcmd(trans, cmd);
|
|
if (ret < 0) {
|
|
if (ret < 0) {
|
|
- IWL_ERR(priv, "Error sending %s: enqueue_hcmd failed: %d\n",
|
|
|
|
|
|
+ IWL_ERR(trans, "Error sending %s: enqueue_hcmd failed: %d\n",
|
|
get_cmd_string(cmd->id), ret);
|
|
get_cmd_string(cmd->id), ret);
|
|
return ret;
|
|
return ret;
|
|
}
|
|
}
|
|
return 0;
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
|
|
-static int iwl_send_cmd_sync(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
|
|
|
|
|
|
+static int iwl_send_cmd_sync(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
|
|
{
|
|
{
|
|
|
|
+ struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
|
int cmd_idx;
|
|
int cmd_idx;
|
|
int ret;
|
|
int ret;
|
|
|
|
|
|
- lockdep_assert_held(&priv->mutex);
|
|
|
|
|
|
+ lockdep_assert_held(&trans->shrd->mutex);
|
|
|
|
|
|
/* A synchronous command can not have a callback set. */
|
|
/* A synchronous command can not have a callback set. */
|
|
if (WARN_ON(cmd->callback))
|
|
if (WARN_ON(cmd->callback))
|
|
return -EINVAL;
|
|
return -EINVAL;
|
|
|
|
|
|
- IWL_DEBUG_INFO(priv, "Attempting to send sync command %s\n",
|
|
|
|
|
|
+ IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n",
|
|
get_cmd_string(cmd->id));
|
|
get_cmd_string(cmd->id));
|
|
|
|
|
|
- set_bit(STATUS_HCMD_ACTIVE, &priv->status);
|
|
|
|
- IWL_DEBUG_INFO(priv, "Setting HCMD_ACTIVE for command %s\n",
|
|
|
|
|
|
+ set_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status);
|
|
|
|
+ IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n",
|
|
get_cmd_string(cmd->id));
|
|
get_cmd_string(cmd->id));
|
|
|
|
|
|
- cmd_idx = iwl_enqueue_hcmd(priv, cmd);
|
|
|
|
|
|
+ cmd_idx = iwl_enqueue_hcmd(trans, cmd);
|
|
if (cmd_idx < 0) {
|
|
if (cmd_idx < 0) {
|
|
ret = cmd_idx;
|
|
ret = cmd_idx;
|
|
- clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
|
|
|
|
- IWL_ERR(priv, "Error sending %s: enqueue_hcmd failed: %d\n",
|
|
|
|
|
|
+ clear_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status);
|
|
|
|
+ IWL_ERR(trans, "Error sending %s: enqueue_hcmd failed: %d\n",
|
|
get_cmd_string(cmd->id), ret);
|
|
get_cmd_string(cmd->id), ret);
|
|
return ret;
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
|
|
- ret = wait_event_interruptible_timeout(priv->wait_command_queue,
|
|
|
|
- !test_bit(STATUS_HCMD_ACTIVE, &priv->status),
|
|
|
|
|
|
+ ret = wait_event_interruptible_timeout(priv(trans)->wait_command_queue,
|
|
|
|
+ !test_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status),
|
|
HOST_COMPLETE_TIMEOUT);
|
|
HOST_COMPLETE_TIMEOUT);
|
|
if (!ret) {
|
|
if (!ret) {
|
|
- if (test_bit(STATUS_HCMD_ACTIVE, &priv->status)) {
|
|
|
|
- IWL_ERR(priv,
|
|
|
|
|
|
+ if (test_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status)) {
|
|
|
|
+ IWL_ERR(trans,
|
|
"Error sending %s: time out after %dms.\n",
|
|
"Error sending %s: time out after %dms.\n",
|
|
get_cmd_string(cmd->id),
|
|
get_cmd_string(cmd->id),
|
|
jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
|
|
jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
|
|
|
|
|
|
- clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
|
|
|
|
- IWL_DEBUG_INFO(priv, "Clearing HCMD_ACTIVE for command"
|
|
|
|
|
|
+ clear_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status);
|
|
|
|
+ IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command"
|
|
"%s\n", get_cmd_string(cmd->id));
|
|
"%s\n", get_cmd_string(cmd->id));
|
|
ret = -ETIMEDOUT;
|
|
ret = -ETIMEDOUT;
|
|
goto cancel;
|
|
goto cancel;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
- if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
|
|
|
|
- IWL_ERR(priv, "Command %s aborted: RF KILL Switch\n",
|
|
|
|
|
|
+ if (test_bit(STATUS_RF_KILL_HW, &trans->shrd->status)) {
|
|
|
|
+ IWL_ERR(trans, "Command %s aborted: RF KILL Switch\n",
|
|
get_cmd_string(cmd->id));
|
|
get_cmd_string(cmd->id));
|
|
ret = -ECANCELED;
|
|
ret = -ECANCELED;
|
|
goto fail;
|
|
goto fail;
|
|
}
|
|
}
|
|
- if (test_bit(STATUS_FW_ERROR, &priv->status)) {
|
|
|
|
- IWL_ERR(priv, "Command %s failed: FW Error\n",
|
|
|
|
|
|
+ if (test_bit(STATUS_FW_ERROR, &trans->shrd->status)) {
|
|
|
|
+ IWL_ERR(trans, "Command %s failed: FW Error\n",
|
|
get_cmd_string(cmd->id));
|
|
get_cmd_string(cmd->id));
|
|
ret = -EIO;
|
|
ret = -EIO;
|
|
goto fail;
|
|
goto fail;
|
|
}
|
|
}
|
|
if ((cmd->flags & CMD_WANT_SKB) && !cmd->reply_page) {
|
|
if ((cmd->flags & CMD_WANT_SKB) && !cmd->reply_page) {
|
|
- IWL_ERR(priv, "Error: Response NULL in '%s'\n",
|
|
|
|
|
|
+ IWL_ERR(trans, "Error: Response NULL in '%s'\n",
|
|
get_cmd_string(cmd->id));
|
|
get_cmd_string(cmd->id));
|
|
ret = -EIO;
|
|
ret = -EIO;
|
|
goto cancel;
|
|
goto cancel;
|
|
@@ -1002,28 +1154,28 @@ cancel:
|
|
* in later, it will possibly set an invalid
|
|
* in later, it will possibly set an invalid
|
|
* address (cmd->meta.source).
|
|
* address (cmd->meta.source).
|
|
*/
|
|
*/
|
|
- priv->txq[priv->cmd_queue].meta[cmd_idx].flags &=
|
|
|
|
|
|
+ trans_pcie->txq[trans->shrd->cmd_queue].meta[cmd_idx].flags &=
|
|
~CMD_WANT_SKB;
|
|
~CMD_WANT_SKB;
|
|
}
|
|
}
|
|
fail:
|
|
fail:
|
|
if (cmd->reply_page) {
|
|
if (cmd->reply_page) {
|
|
- iwl_free_pages(priv, cmd->reply_page);
|
|
|
|
|
|
+ iwl_free_pages(trans->shrd, cmd->reply_page);
|
|
cmd->reply_page = 0;
|
|
cmd->reply_page = 0;
|
|
}
|
|
}
|
|
|
|
|
|
return ret;
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
|
|
-int iwl_send_cmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
|
|
|
|
|
|
+int iwl_trans_pcie_send_cmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
|
|
{
|
|
{
|
|
if (cmd->flags & CMD_ASYNC)
|
|
if (cmd->flags & CMD_ASYNC)
|
|
- return iwl_send_cmd_async(priv, cmd);
|
|
|
|
|
|
+ return iwl_send_cmd_async(trans, cmd);
|
|
|
|
|
|
- return iwl_send_cmd_sync(priv, cmd);
|
|
|
|
|
|
+ return iwl_send_cmd_sync(trans, cmd);
|
|
}
|
|
}
|
|
|
|
|
|
-int iwl_send_cmd_pdu(struct iwl_priv *priv, u8 id, u32 flags, u16 len,
|
|
|
|
- const void *data)
|
|
|
|
|
|
+int iwl_trans_pcie_send_cmd_pdu(struct iwl_trans *trans, u8 id, u32 flags,
|
|
|
|
+ u16 len, const void *data)
|
|
{
|
|
{
|
|
struct iwl_host_cmd cmd = {
|
|
struct iwl_host_cmd cmd = {
|
|
.id = id,
|
|
.id = id,
|
|
@@ -1032,5 +1184,53 @@ int iwl_send_cmd_pdu(struct iwl_priv *priv, u8 id, u32 flags, u16 len,
|
|
.flags = flags,
|
|
.flags = flags,
|
|
};
|
|
};
|
|
|
|
|
|
- return iwl_send_cmd(priv, &cmd);
|
|
|
|
|
|
+ return iwl_trans_pcie_send_cmd(trans, &cmd);
|
|
|
|
+}
|
|
|
|
+
|
|
|
|
+/* Frees buffers until index _not_ inclusive */
|
|
|
|
+int iwl_tx_queue_reclaim(struct iwl_trans *trans, int txq_id, int index,
|
|
|
|
+ struct sk_buff_head *skbs)
|
|
|
|
+{
|
|
|
|
+ struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
|
|
|
+ struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
|
|
|
|
+ struct iwl_queue *q = &txq->q;
|
|
|
|
+ int last_to_free;
|
|
|
|
+ int freed = 0;
|
|
|
|
+
|
|
|
|
+ /*Since we free until index _not_ inclusive, the one before index is
|
|
|
|
+ * the last we will free. This one must be used */
|
|
|
|
+ last_to_free = iwl_queue_dec_wrap(index, q->n_bd);
|
|
|
|
+
|
|
|
|
+ if ((index >= q->n_bd) ||
|
|
|
|
+ (iwl_queue_used(q, last_to_free) == 0)) {
|
|
|
|
+ IWL_ERR(trans, "%s: Read index for DMA queue txq id (%d), "
|
|
|
|
+ "last_to_free %d is out of range [0-%d] %d %d.\n",
|
|
|
|
+ __func__, txq_id, last_to_free, q->n_bd,
|
|
|
|
+ q->write_ptr, q->read_ptr);
|
|
|
|
+ return 0;
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
+ IWL_DEBUG_TX_REPLY(trans, "reclaim: [%d, %d, %d]\n", txq_id,
|
|
|
|
+ q->read_ptr, index);
|
|
|
|
+
|
|
|
|
+ if (WARN_ON(!skb_queue_empty(skbs)))
|
|
|
|
+ return 0;
|
|
|
|
+
|
|
|
|
+ for (;
|
|
|
|
+ q->read_ptr != index;
|
|
|
|
+ q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
|
|
|
|
+
|
|
|
|
+ if (WARN_ON_ONCE(txq->skbs[txq->q.read_ptr] == NULL))
|
|
|
|
+ continue;
|
|
|
|
+
|
|
|
|
+ __skb_queue_tail(skbs, txq->skbs[txq->q.read_ptr]);
|
|
|
|
+
|
|
|
|
+ txq->skbs[txq->q.read_ptr] = NULL;
|
|
|
|
+
|
|
|
|
+ iwlagn_txq_inval_byte_cnt_tbl(trans, txq);
|
|
|
|
+
|
|
|
|
+ iwlagn_txq_free_tfd(trans, txq, txq->q.read_ptr);
|
|
|
|
+ freed++;
|
|
|
|
+ }
|
|
|
|
+ return freed;
|
|
}
|
|
}
|