sh: Add SH-2A platform headers.

Mostly SH-2 wrappers..

Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>

include/asm-sh/bugs.h

@@ -23,9 +23,13 @@ static void __init check_bugs(void)
 	cpu_data->loops_per_jiffy = loops_per_jiffy;
 
 	switch (cpu_data->type) {
-	case CPU_SH7604:
+	case CPU_SH7604 ... CPU_SH7619:
 		*p++ = '2';
 		break;
+	case CPU_SH7206:
+		*p++ = '2';
+		*p++ = 'a';
+		break;
 	case CPU_SH7705 ... CPU_SH7300:
 		*p++ = '3';
 		break;

include/asm-sh/cpu-sh2/cache.h

@@ -12,6 +12,7 @@
 
 #define L1_CACHE_SHIFT	4
 
+#if defined(CONFIG_CPU_SUBTYPE_SH7604)
 #define CCR		0xfffffe92	/* Address of Cache Control Register */
 
 #define CCR_CACHE_CE	0x01	/* Cache enable */
@@ -27,5 +28,26 @@
 #define CCR_CACHE_ORA		CCR_CACHE_TW
 #define CCR_CACHE_WT		0x00	/* SH-2 is _always_ write-through */
 
+#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
+#define CCR1		0xffffffec
+#define CCR		CCR1
+
+#define CCR_CACHE_CE	0x01	/* Cache enable */
+#define CCR_CACHE_WT	0x06    /* CCR[bit1=1,bit2=1] */
+				/* 0x00000000-0x7fffffff: Write-through  */
+				/* 0x80000000-0x9fffffff: Write-back     */
+                                /* 0xc0000000-0xdfffffff: Write-through  */
+#define CCR_CACHE_CB	0x00    /* CCR[bit1=0,bit2=0] */
+				/* 0x00000000-0x7fffffff: Write-back     */
+				/* 0x80000000-0x9fffffff: Write-through  */
+                                /* 0xc0000000-0xdfffffff: Write-back     */
+#define CCR_CACHE_CF	0x08	/* Cache invalidate */
+
+#define CACHE_OC_ADDRESS_ARRAY	0xf0000000
+#define CACHE_OC_DATA_ARRAY	0xf1000000
+
+#define CCR_CACHE_ENABLE	CCR_CACHE_CE
+#define CCR_CACHE_INVALIDATE	CCR_CACHE_CF
+#endif
 #endif /* __ASM_CPU_SH2_CACHE_H */
 

include/asm-sh/cpu-sh2/freq.h

@@ -0,0 +1,18 @@
+/*
+ * include/asm-sh/cpu-sh2/freq.h
+ *
+ * Copyright (C) 2006  Yoshinori Sato
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH2_FREQ_H
+#define __ASM_CPU_SH2_FREQ_H
+
+#if defined(CONFIG_CPU_SUBTYPE_SH7619)
+#define FREQCR	0xf815ff80
+#endif
+
+#endif /* __ASM_CPU_SH2_FREQ_H */
+

include/asm-sh/cpu-sh2/irq.h

@@ -0,0 +1,84 @@
+#ifndef __ASM_SH_CPU_SH2_IRQ_H
+#define __ASM_SH_CPU_SH2_IRQ_H
+
+/*
+ *
+ * linux/include/asm-sh/cpu-sh2/irq.h
+ *
+ * Copyright (C) 1999  Niibe Yutaka & Takeshi Yaegashi
+ * Copyright (C) 2000  Kazumoto Kojima
+ * Copyright (C) 2003  Paul Mundt
+ *
+ */
+
+#include <linux/config.h>
+
+#if defined(CONFIG_CPU_SUBTYPE_SH7044)
+#define INTC_IPRA	0xffff8348UL
+#define INTC_IPRB	0xffff834aUL
+#define INTC_IPRC	0xffff834cUL
+#define INTC_IPRD	0xffff834eUL
+#define INTC_IPRE	0xffff8350UL
+#define INTC_IPRF	0xffff8352UL
+#define INTC_IPRG	0xffff8354UL
+#define INTC_IPRH	0xffff8356UL
+
+#define INTC_ICR	0xffff8358UL
+#define INTC_ISR	0xffff835aUL
+#elif defined(CONFIG_CPU_SUBTYPE_SH7604)
+#define INTC_IPRA	0xfffffee2UL
+#define INTC_IPRB	0xfffffe60UL
+
+#define INTC_VCRA	0xfffffe62UL
+#define INTC_VCRB	0xfffffe64UL
+#define INTC_VCRC	0xfffffe66UL
+#define INTC_VCRD	0xfffffe68UL
+
+#define INTC_VCRWDT	0xfffffee4UL
+#define INTC_VCRDIV	0xffffff0cUL
+#define INTC_VCRDMA0	0xffffffa0UL
+#define INTC_VCRDMA1	0xffffffa8UL
+
+#define INTC_ICR	0xfffffee0UL
+#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
+#define INTC_IPRA	0xf8140006UL
+#define INTC_IPRB	0xf8140008UL
+#define INTC_IPRC	0xf8080000UL
+#define INTC_IPRD	0xf8080002UL
+#define INTC_IPRE	0xf8080004UL
+#define INTC_IPRF	0xf8080006UL
+#define INTC_IPRG	0xf8080008UL
+
+#define INTC_ICR0	0xf8140000UL
+#define INTC_IRQCR	0xf8140002UL
+#define INTC_IRQSR	0xf8140004UL
+
+#define CMI0_IRQ	86
+#define CMI1_IRQ	87
+
+#define SCIF_ERI_IRQ	88
+#define SCIF_RXI_IRQ	89
+#define SCIF_BRI_IRQ	90
+#define SCIF_TXI_IRQ	91
+#define SCIF_IPR_ADDR	INTC_IPRD
+#define SCIF_IPR_POS	3
+#define SCIF_PRIORITY	3
+
+#define SCIF1_ERI_IRQ	92
+#define SCIF1_RXI_IRQ	93
+#define SCIF1_BRI_IRQ	94
+#define SCIF1_TXI_IRQ	95
+#define SCIF1_IPR_ADDR	INTC_IPRD
+#define SCIF1_IPR_POS	2
+#define SCIF1_PRIORITY	3
+
+#define SCIF2_BRI_IRQ	96
+#define SCIF2_RXI_IRQ	97
+#define SCIF2_ERI_IRQ	98
+#define SCIF2_TXI_IRQ	99
+#define SCIF2_IPR_ADDR	INTC_IPRD
+#define SCIF2_IPR_POS	1
+#define SCIF2_PRIORITY	3
+#endif
+
+#endif /* __ASM_SH_CPU_SH2_IRQ_H */

include/asm-sh/cpu-sh2/mmu_context.h

@@ -0,0 +1,16 @@
+/*
+ * include/asm-sh/cpu-sh2/mmu_context.h
+ *
+ * Copyright (C) 2003  Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH2_MMU_CONTEXT_H
+#define __ASM_CPU_SH2_MMU_CONTEXT_H
+
+/* No MMU */
+
+#endif /* __ASM_CPU_SH2_MMU_CONTEXT_H */
+

include/asm-sh/cpu-sh2a/addrspace.h

@@ -0,0 +1 @@
+#include <asm/cpu-sh2/addrspace.h>

include/asm-sh/cpu-sh2a/cache.h

@@ -0,0 +1,39 @@
+/*
+ * include/asm-sh/cpu-sh2a/cache.h
+ *
+ * Copyright (C) 2004 Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH2A_CACHE_H
+#define __ASM_CPU_SH2A_CACHE_H
+
+#define L1_CACHE_SHIFT	4
+
+#define CCR1		0xfffc1000
+#define CCR2		0xfffc1004
+
+/* CCR1 behaves more like the traditional CCR */
+#define CCR		CCR1
+
+/*
+ * Most of the SH-2A CCR1 definitions resemble the SH-4 ones. All others not
+ * listed here are reserved.
+ */
+#define CCR_CACHE_CB	0x0000	/* Hack */
+#define CCR_CACHE_OCE	0x0001
+#define CCR_CACHE_WT	0x0002
+#define CCR_CACHE_OCI	0x0008	/* OCF */
+#define CCR_CACHE_ICE	0x0100
+#define CCR_CACHE_ICI	0x0800	/* ICF */
+
+#define CACHE_IC_ADDRESS_ARRAY	0xf0000000
+#define CACHE_OC_ADDRESS_ARRAY	0xf0800000
+
+#define CCR_CACHE_ENABLE	(CCR_CACHE_OCE | CCR_CACHE_ICE)
+#define CCR_CACHE_INVALIDATE	(CCR_CACHE_OCI | CCR_CACHE_ICI)
+
+#endif /* __ASM_CPU_SH2A_CACHE_H */
+

include/asm-sh/cpu-sh2a/cacheflush.h

@@ -0,0 +1 @@
+#include <asm/cpu-sh2/cacheflush.h>

include/asm-sh/cpu-sh2a/dma.h

@@ -0,0 +1 @@
+#include <asm/cpu-sh2/dma.h>

include/asm-sh/cpu-sh2a/freq.h

@@ -0,0 +1,18 @@
+/*
+ * include/asm-sh/cpu-sh2a/freq.h
+ *
+ * Copyright (C) 2006  Yoshinori Sato
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH2A_FREQ_H
+#define __ASM_CPU_SH2A_FREQ_H
+
+#if defined(CONFIG_CPU_SUBTYPE_SH7206)
+#define FREQCR	0xfffe0010
+#endif
+
+#endif /* __ASM_CPU_SH2A_FREQ_H */
+

include/asm-sh/cpu-sh2a/irq.h

@@ -0,0 +1,75 @@
+#ifndef __ASM_SH_CPU_SH2A_IRQ_H
+#define __ASM_SH_CPU_SH2A_IRQ_H
+
+#define INTC_IPR01	0xfffe0818UL
+#define INTC_IPR02	0xfffe081aUL
+#define INTC_IPR05	0xfffe0820UL
+#define INTC_IPR06	0xfffe0c00UL
+#define INTC_IPR07	0xfffe0c02UL
+#define INTC_IPR08	0xfffe0c04UL
+#define INTC_IPR09	0xfffe0c06UL
+#define INTC_IPR10	0xfffe0c08UL
+#define INTC_IPR11	0xfffe0c0aUL
+#define INTC_IPR12	0xfffe0c0cUL
+#define INTC_IPR13	0xfffe0c0eUL
+#define INTC_IPR14	0xfffe0c10UL
+
+#define INTC_ICR0	0xfffe0800UL
+#define INTC_ICR1	0xfffe0802UL
+#define INTC_ICR2	0xfffe0804UL
+#define INTC_ISR	0xfffe0806UL
+
+#define IRQ0_IRQ	64
+#define IRQ1_IRQ	65
+#define IRQ2_IRQ	66
+#define IRQ3_IRQ	67
+#define IRQ4_IRQ	68
+#define IRQ5_IRQ	69
+#define IRQ6_IRQ	70
+#define IRQ7_IRQ	71
+
+#define PINT0_IRQ	80
+#define PINT1_IRQ	81
+#define PINT2_IRQ	82
+#define PINT3_IRQ	83
+#define PINT4_IRQ	84
+#define PINT5_IRQ	85
+#define PINT6_IRQ	86
+#define PINT7_IRQ	87
+
+#define CMI0_IRQ	140
+#define CMI1_IRQ	141
+
+#define SCIF_BRI_IRQ	240
+#define SCIF_ERI_IRQ	241
+#define SCIF_RXI_IRQ	242
+#define SCIF_TXI_IRQ	243
+#define SCIF_IPR_ADDR	INTC_IPR14
+#define SCIF_IPR_POS	3
+#define SCIF_PRIORITY	3
+
+#define SCIF1_BRI_IRQ	244
+#define SCIF1_ERI_IRQ	245
+#define SCIF1_RXI_IRQ	246
+#define SCIF1_TXI_IRQ	247
+#define SCIF1_IPR_ADDR	INTC_IPR14
+#define SCIF1_IPR_POS	2
+#define SCIF1_PRIORITY	3
+
+#define SCIF2_BRI_IRQ	248
+#define SCIF2_ERI_IRQ	249
+#define SCIF2_RXI_IRQ	250
+#define SCIF2_TXI_IRQ	251
+#define SCIF2_IPR_ADDR	INTC_IPR14
+#define SCIF2_IPR_POS	1
+#define SCIF2_PRIORITY	3
+
+#define SCIF3_BRI_IRQ	252
+#define SCIF3_ERI_IRQ	253
+#define SCIF3_RXI_IRQ	254
+#define SCIF3_TXI_IRQ	255
+#define SCIF3_IPR_ADDR	INTC_IPR14
+#define SCIF3_IPR_POS	0
+#define SCIF3_PRIORITY	3
+
+#endif /* __ASM_SH_CPU_SH2A_IRQ_H */

include/asm-sh/cpu-sh2a/mmu_context.h

@@ -0,0 +1 @@
+#include <asm/cpu-sh2/mmu_context.h>

include/asm-sh/cpu-sh2a/timer.h

@@ -0,0 +1 @@
+#include <asm/cpu-sh2/timer.h>

include/asm-sh/cpu-sh2a/ubc.h

@@ -0,0 +1 @@
+#include <asm/cpu-sh2/ubc.h>

include/asm-sh/cpu-sh2a/watchdog.h

@@ -0,0 +1 @@
+#include <asm/cpu-sh2/watchdog.h>

include/asm-sh/entry-macros.S

@@ -0,0 +1,32 @@
+! entry.S macro define
+	
+	.macro	cli
+	stc	sr, r0
+	or	#0xf0, r0
+	ldc	r0, sr
+	.endm
+
+	.macro	sti
+	mov	#0xf0, r11
+	extu.b	r11, r11
+	not	r11, r11
+	stc	sr, r10
+	and	r11, r10
+#ifdef CONFIG_HAS_SR_RB
+	stc	k_g_imask, r11
+	or	r11, r10
+#endif
+	ldc	r10, sr
+	.endm
+
+	.macro	get_current_thread_info, ti, tmp
+#ifdef CONFIG_HAS_SR_RB
+	stc	r7_bank, \ti
+#else
+	mov	#((THREAD_SIZE - 1)>> 8) ^ 0xff, \tmp
+	shll8	\tmp
+	mov	r15, \ti
+	and	\tmp, \ti
+#endif	
+	.endm
+

include/asm-sh/irq.h

@@ -14,6 +14,10 @@
 #include <asm/machvec.h>
 #include <asm/ptrace.h>		/* for pt_regs */
 
+#if defined(CONFIG_CPU_SH2)
+#include <asm/cpu/irq.h>
+#endif
+
 #ifndef CONFIG_CPU_SUBTYPE_SH7780
 
 #define INTC_DMAC0_MSK	0
@@ -28,6 +32,31 @@
 #define INTC_IPRD	0xffd00010UL
 #endif
 
+#if defined(CONFIG_CPU_SUBTYPE_SH7206)
+#ifdef CONFIG_SH_CMT
+#define TIMER_IRQ	CMI0_IRQ
+#define TIMER_IPR_ADDR	INTC_IPR08
+#define TIMER_IPR_POS	 3
+#define TIMER_PRIORITY	 2
+
+#define TIMER1_IRQ	CMI1_IRQ
+#define TIMER1_IPR_ADDR	INTC_IPR08
+#define TIMER1_IPR_POS	 2
+#define TIMER1_PRIORITY	 2
+#endif
+
+#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
+#define TIMER_IRQ	CMI0_IRQ
+#define TIMER_IPR_ADDR	INTC_IPRC
+#define TIMER_IPR_POS	 1
+#define TIMER_PRIORITY	 2
+
+#define TIMER1_IRQ	CMI1_IRQ
+#define TIMER1_IPR_ADDR	INTC_IPRC
+#define TIMER1_IPR_POS	 0
+#define TIMER1_PRIORITY	 4
+
+#else
 #define TIMER_IRQ	16
 #define TIMER_IPR_ADDR	INTC_IPRA
 #define TIMER_IPR_POS	 3
@@ -37,11 +66,14 @@
 #define TIMER1_IPR_ADDR	INTC_IPRA
 #define TIMER1_IPR_POS	 2
 #define TIMER1_PRIORITY	 4
+#endif
 
+#if !defined(CONFIG_CPU_SH2)
 #define RTC_IRQ		22
 #define RTC_IPR_ADDR	INTC_IPRA
 #define RTC_IPR_POS	 0
 #define RTC_PRIORITY	TIMER_PRIORITY
+#endif
 
 #if defined(CONFIG_CPU_SH3)
 #define DMTE0_IRQ	48
@@ -265,6 +297,10 @@
 # define ONCHIP_NR_IRQS 109
 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
 # define ONCHIP_NR_IRQS 111
+#elif defined(CONFIG_CPU_SUBTYPE_SH7206)
+# define ONCHIP_NR_IRQS 256
+#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
+# define ONCHIP_NR_IRQS 128
 #elif defined(CONFIG_SH_UNKNOWN)	/* Most be last */
 # define ONCHIP_NR_IRQS 144
 #endif
@@ -322,6 +358,40 @@ extern void enable_irq(unsigned int);
 extern void make_maskreg_irq(unsigned int irq);
 extern unsigned short *irq_mask_register;
 
+#if defined(CONFIG_CPU_SUBTYPE_SH7619)
+#define IRQ0_IRQ	16
+#define IRQ1_IRQ	17
+#define IRQ2_IRQ	18
+#define IRQ3_IRQ	19
+#define IRQ4_IRQ	32
+#define IRQ5_IRQ	33
+#define IRQ6_IRQ	34
+#define IRQ7_IRQ	35
+#elif !defined(CONFIG_CPU_SUBTYPE_SH7206)
+#define IRQ0_IRQ	32
+#define IRQ1_IRQ	33
+#define IRQ2_IRQ	34
+#define IRQ3_IRQ	35
+#define IRQ4_IRQ	36
+#define IRQ5_IRQ	37
+#endif
+
+#define IRQ0_PRIORITY	1
+#define IRQ1_PRIORITY	1
+#define IRQ2_PRIORITY	1
+#define IRQ3_PRIORITY	1
+#define IRQ4_PRIORITY	1
+#define IRQ5_PRIORITY	1
+
+#ifndef IRQ0_IPR_POS
+#define IRQ0_IPR_POS	0
+#define IRQ1_IPR_POS	1
+#define IRQ2_IPR_POS	2
+#define IRQ3_IPR_POS	3
+#define IRQ4_IPR_POS	0
+#define IRQ5_IPR_POS	1
+#endif
+
 /*
  * PINT IRQs
  */

include/asm-sh/processor.h

@@ -36,7 +36,10 @@
  */
 enum cpu_type {
 	/* SH-2 types */
-	CPU_SH7604,
+	CPU_SH7604, CPU_SH7619,
+
+	/* SH-2A types */
+	CPU_SH7206,
 
 	/* SH-3 types */
 	CPU_SH7705, CPU_SH7706, CPU_SH7707,

include/asm-sh/unistd.h

@@ -349,12 +349,30 @@ do { \
 	return (type) (res); \
 } while (0)
 
+#if defined(__sh2__) || defined(__SH2E__) || defined(__SH2A__)
+#define SYSCALL_ARG0	"trapa #0x20"
+#define SYSCALL_ARG1	"trapa #0x21"
+#define SYSCALL_ARG2	"trapa #0x22"
+#define SYSCALL_ARG3	"trapa #0x23"
+#define SYSCALL_ARG4	"trapa #0x24"
+#define SYSCALL_ARG5	"trapa #0x25"
+#define SYSCALL_ARG6	"trapa #0x26"
+#else
+#define SYSCALL_ARG0	"trapa #0x10"
+#define SYSCALL_ARG1	"trapa #0x11"
+#define SYSCALL_ARG2	"trapa #0x12"
+#define SYSCALL_ARG3	"trapa #0x13"
+#define SYSCALL_ARG4	"trapa #0x14"
+#define SYSCALL_ARG5	"trapa #0x15"
+#define SYSCALL_ARG6	"trapa #0x16"
+#endif
+
 /* XXX - _foo needs to be __foo, while __NR_bar could be _NR_bar. */
 #define _syscall0(type,name) \
 type name(void) \
 { \
 register long __sc0 __asm__ ("r3") = __NR_##name; \
-__asm__ __volatile__ ("trapa	#0x10" \
+__asm__ __volatile__ (SYSCALL_ARG0 \
 	: "=z" (__sc0) \
 	: "0" (__sc0) \
 	: "memory" ); \
@@ -366,7 +384,7 @@ type name(type1 arg1) \
 { \
 register long __sc0 __asm__ ("r3") = __NR_##name; \
 register long __sc4 __asm__ ("r4") = (long) arg1; \
-__asm__ __volatile__ ("trapa	#0x11" \
+__asm__ __volatile__ (SYSCALL_ARG1 \
 	: "=z" (__sc0) \
 	: "0" (__sc0), "r" (__sc4) \
 	: "memory"); \
@@ -379,7 +397,7 @@ type name(type1 arg1,type2 arg2) \
 register long __sc0 __asm__ ("r3") = __NR_##name; \
 register long __sc4 __asm__ ("r4") = (long) arg1; \
 register long __sc5 __asm__ ("r5") = (long) arg2; \
-__asm__ __volatile__ ("trapa	#0x12" \
+__asm__ __volatile__ (SYSCALL_ARG2 \
 	: "=z" (__sc0) \
 	: "0" (__sc0), "r" (__sc4), "r" (__sc5) \
 	: "memory"); \
@@ -393,7 +411,7 @@ register long __sc0 __asm__ ("r3") = __NR_##name; \
 register long __sc4 __asm__ ("r4") = (long) arg1; \
 register long __sc5 __asm__ ("r5") = (long) arg2; \
 register long __sc6 __asm__ ("r6") = (long) arg3; \
-__asm__ __volatile__ ("trapa	#0x13" \
+__asm__ __volatile__ (SYSCALL_ARG3 \
 	: "=z" (__sc0) \
 	: "0" (__sc0), "r" (__sc4), "r" (__sc5), "r" (__sc6) \
 	: "memory"); \
@@ -408,7 +426,7 @@ register long __sc4 __asm__ ("r4") = (long) arg1; \
 register long __sc5 __asm__ ("r5") = (long) arg2; \
 register long __sc6 __asm__ ("r6") = (long) arg3; \
 register long __sc7 __asm__ ("r7") = (long) arg4; \
-__asm__ __volatile__ ("trapa	#0x14" \
+__asm__ __volatile__ (SYSCALL_ARG4 \
 	: "=z" (__sc0) \
 	: "0" (__sc0), "r" (__sc4), "r" (__sc5), "r" (__sc6),  \
 	  "r" (__sc7) \
@@ -425,7 +443,7 @@ register long __sc5 __asm__ ("r5") = (long) arg2; \
 register long __sc6 __asm__ ("r6") = (long) arg3; \
 register long __sc7 __asm__ ("r7") = (long) arg4; \
 register long __sc0 __asm__ ("r0") = (long) arg5; \
-__asm__ __volatile__ ("trapa	#0x15" \
+__asm__ __volatile__ (SYSCALL_ARG5 \
 	: "=z" (__sc0) \
 	: "0" (__sc0), "r" (__sc4), "r" (__sc5), "r" (__sc6), "r" (__sc7),  \
 	  "r" (__sc3) \
@@ -443,7 +461,7 @@ register long __sc6 __asm__ ("r6") = (long) arg3; \
 register long __sc7 __asm__ ("r7") = (long) arg4; \
 register long __sc0 __asm__ ("r0") = (long) arg5; \
 register long __sc1 __asm__ ("r1") = (long) arg6; \
-__asm__ __volatile__ ("trapa	#0x16" \
+__asm__ __volatile__ (SYSCALL_ARG6 \
 	: "=z" (__sc0) \
 	: "0" (__sc0), "r" (__sc4), "r" (__sc5), "r" (__sc6), "r" (__sc7),  \
 	  "r" (__sc3), "r" (__sc1) \