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@@ -1887,14 +1887,13 @@
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#define _PIPE_CRC_RES_RES2_A_G4X (dev_priv->info->display_mmio_offset + 0x60080)
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/* Pipe B CRC regs */
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-#define _PIPE_CRC_CTL_B 0x61050
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#define _PIPE_CRC_RES_1_B_IVB 0x61064
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#define _PIPE_CRC_RES_2_B_IVB 0x61068
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#define _PIPE_CRC_RES_3_B_IVB 0x6106c
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#define _PIPE_CRC_RES_4_B_IVB 0x61070
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#define _PIPE_CRC_RES_5_B_IVB 0x61074
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-#define PIPE_CRC_CTL(pipe) _PIPE(pipe, _PIPE_CRC_CTL_A, _PIPE_CRC_CTL_B)
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+#define PIPE_CRC_CTL(pipe) _PIPE_INC(pipe, _PIPE_CRC_CTL_A, 0x01000)
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#define PIPE_CRC_RES_1_IVB(pipe) \
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_PIPE(pipe, _PIPE_CRC_RES_1_A_IVB, _PIPE_CRC_RES_1_B_IVB)
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#define PIPE_CRC_RES_2_IVB(pipe) \
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