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@@ -2574,7 +2574,8 @@ static int valleyview_irq_postinstall(struct drm_device *dev)
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{
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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u32 enable_mask;
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- u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
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+ u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV |
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+ PIPE_CRC_DONE_ENABLE;
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unsigned long irqflags;
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enable_mask = I915_DISPLAY_PORT_INTERRUPT;
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@@ -2697,6 +2698,7 @@ static void i8xx_irq_preinstall(struct drm_device * dev)
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static int i8xx_irq_postinstall(struct drm_device *dev)
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{
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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+ unsigned long irqflags;
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I915_WRITE16(EMR,
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~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
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@@ -2717,6 +2719,13 @@ static int i8xx_irq_postinstall(struct drm_device *dev)
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I915_USER_INTERRUPT);
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POSTING_READ16(IER);
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+ /* Interrupt setup is already guaranteed to be single-threaded, this is
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+ * just to make the assert_spin_locked check happy. */
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+ spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
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+ i915_enable_pipestat(dev_priv, 0, PIPE_CRC_DONE_ENABLE);
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+ i915_enable_pipestat(dev_priv, 1, PIPE_CRC_DONE_ENABLE);
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+ spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
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+
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return 0;
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}
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@@ -2857,6 +2866,7 @@ static int i915_irq_postinstall(struct drm_device *dev)
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{
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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u32 enable_mask;
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+ unsigned long irqflags;
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I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
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@@ -2892,6 +2902,13 @@ static int i915_irq_postinstall(struct drm_device *dev)
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i915_enable_asle_pipestat(dev);
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+ /* Interrupt setup is already guaranteed to be single-threaded, this is
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+ * just to make the assert_spin_locked check happy. */
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+ spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
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+ i915_enable_pipestat(dev_priv, 0, PIPE_CRC_DONE_ENABLE);
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+ i915_enable_pipestat(dev_priv, 1, PIPE_CRC_DONE_ENABLE);
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+ spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
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+
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return 0;
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}
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@@ -3105,6 +3122,8 @@ static int i965_irq_postinstall(struct drm_device *dev)
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* just to make the assert_spin_locked check happy. */
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spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
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i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
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+ i915_enable_pipestat(dev_priv, 0, PIPE_CRC_DONE_ENABLE);
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+ i915_enable_pipestat(dev_priv, 1, PIPE_CRC_DONE_ENABLE);
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spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
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/*
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