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@@ -134,6 +134,7 @@ enum {
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PORT_IRQ_D2H_REG_FIS,
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/* PORT_CMD bits */
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+ PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
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PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
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PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
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PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
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@@ -441,7 +442,7 @@ static void ahci_phy_reset(struct ata_port *ap)
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void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
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struct ata_taskfile tf;
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struct ata_device *dev = &ap->device[0];
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- u32 tmp;
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+ u32 new_tmp, tmp;
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__sata_phy_reset(ap);
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@@ -455,8 +456,21 @@ static void ahci_phy_reset(struct ata_port *ap)
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tf.nsect = (tmp) & 0xff;
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dev->class = ata_dev_classify(&tf);
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- if (!ata_dev_present(dev))
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+ if (!ata_dev_present(dev)) {
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ata_port_disable(ap);
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+ return;
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+ }
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+
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+ /* Make sure port's ATAPI bit is set appropriately */
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+ new_tmp = tmp = readl(port_mmio + PORT_CMD);
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+ if (dev->class == ATA_DEV_ATAPI)
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+ new_tmp |= PORT_CMD_ATAPI;
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+ else
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+ new_tmp &= ~PORT_CMD_ATAPI;
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+ if (new_tmp != tmp) {
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+ writel(new_tmp, port_mmio + PORT_CMD);
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+ readl(port_mmio + PORT_CMD); /* flush */
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+ }
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}
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static u8 ahci_check_status(struct ata_port *ap)
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@@ -474,11 +488,12 @@ static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
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ata_tf_from_fis(d2h_fis, tf);
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}
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-static void ahci_fill_sg(struct ata_queued_cmd *qc)
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+static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc)
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{
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struct ahci_port_priv *pp = qc->ap->private_data;
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struct scatterlist *sg;
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struct ahci_sg *ahci_sg;
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+ unsigned int n_sg = 0;
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VPRINTK("ENTER\n");
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@@ -493,8 +508,12 @@ static void ahci_fill_sg(struct ata_queued_cmd *qc)
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ahci_sg->addr = cpu_to_le32(addr & 0xffffffff);
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ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
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ahci_sg->flags_size = cpu_to_le32(sg_len - 1);
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+
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ahci_sg++;
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+ n_sg++;
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}
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+
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+ return n_sg;
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}
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static void ahci_qc_prep(struct ata_queued_cmd *qc)
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@@ -503,13 +522,14 @@ static void ahci_qc_prep(struct ata_queued_cmd *qc)
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struct ahci_port_priv *pp = ap->private_data;
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u32 opts;
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const u32 cmd_fis_len = 5; /* five dwords */
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+ unsigned int n_elem;
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/*
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* Fill in command slot information (currently only one slot,
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* slot 0, is currently since we don't do queueing)
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*/
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- opts = (qc->n_elem << 16) | cmd_fis_len;
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+ opts = cmd_fis_len;
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if (qc->tf.flags & ATA_TFLAG_WRITE)
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opts |= AHCI_CMD_WRITE;
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if (is_atapi_taskfile(&qc->tf))
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@@ -533,7 +553,9 @@ static void ahci_qc_prep(struct ata_queued_cmd *qc)
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if (!(qc->flags & ATA_QCFLAG_DMAMAP))
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return;
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- ahci_fill_sg(qc);
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+ n_elem = ahci_fill_sg(qc);
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+
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+ pp->cmd_slot[0].opts |= cpu_to_le32(n_elem << 16);
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}
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static void ahci_intr_error(struct ata_port *ap, u32 irq_stat)
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