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@@ -134,6 +134,7 @@ enum {
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PORT_IRQ_D2H_REG_FIS,
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/* PORT_CMD bits */
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+ PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
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PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
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PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
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PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
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@@ -441,7 +442,7 @@ static void ahci_phy_reset(struct ata_port *ap)
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void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
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struct ata_taskfile tf;
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struct ata_device *dev = &ap->device[0];
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- u32 tmp;
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+ u32 new_tmp, tmp;
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__sata_phy_reset(ap);
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@@ -455,8 +456,21 @@ static void ahci_phy_reset(struct ata_port *ap)
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tf.nsect = (tmp) & 0xff;
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dev->class = ata_dev_classify(&tf);
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- if (!ata_dev_present(dev))
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+ if (!ata_dev_present(dev)) {
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ata_port_disable(ap);
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+ return;
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+ }
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+
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+ /* Make sure port's ATAPI bit is set appropriately */
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+ new_tmp = tmp = readl(port_mmio + PORT_CMD);
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+ if (dev->class == ATA_DEV_ATAPI)
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+ new_tmp |= PORT_CMD_ATAPI;
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+ else
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+ new_tmp &= ~PORT_CMD_ATAPI;
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+ if (new_tmp != tmp) {
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+ writel(new_tmp, port_mmio + PORT_CMD);
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+ readl(port_mmio + PORT_CMD); /* flush */
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+ }
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}
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static u8 ahci_check_status(struct ata_port *ap)
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