|
@@ -53,9 +53,9 @@ static struct clk extalt_clkin_ck = {
|
|
|
static struct clk pad_clks_ck = {
|
|
|
.name = "pad_clks_ck",
|
|
|
.rate = 12000000,
|
|
|
- .ops = &clkops_omap2_dflt,
|
|
|
- .enable_reg = OMAP4430_CM_CLKSEL_ABE,
|
|
|
- .enable_bit = OMAP4430_PAD_CLKS_GATE_SHIFT,
|
|
|
+ .ops = &clkops_omap2_dflt,
|
|
|
+ .enable_reg = OMAP4430_CM_CLKSEL_ABE,
|
|
|
+ .enable_bit = OMAP4430_PAD_CLKS_GATE_SHIFT,
|
|
|
};
|
|
|
|
|
|
static struct clk pad_slimbus_core_clks_ck = {
|
|
@@ -73,9 +73,9 @@ static struct clk secure_32k_clk_src_ck = {
|
|
|
static struct clk slimbus_clk = {
|
|
|
.name = "slimbus_clk",
|
|
|
.rate = 12000000,
|
|
|
- .ops = &clkops_omap2_dflt,
|
|
|
- .enable_reg = OMAP4430_CM_CLKSEL_ABE,
|
|
|
- .enable_bit = OMAP4430_SLIMBUS_CLK_GATE_SHIFT,
|
|
|
+ .ops = &clkops_omap2_dflt,
|
|
|
+ .enable_reg = OMAP4430_CM_CLKSEL_ABE,
|
|
|
+ .enable_bit = OMAP4430_SLIMBUS_CLK_GATE_SHIFT,
|
|
|
};
|
|
|
|
|
|
static struct clk sys_32k_ck = {
|
|
@@ -258,8 +258,8 @@ static struct dpll_data dpll_abe_dd = {
|
|
|
.enable_mask = OMAP4430_DPLL_EN_MASK,
|
|
|
.autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
|
|
|
.idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
|
|
|
- .max_multiplier = OMAP4430_MAX_DPLL_MULT,
|
|
|
- .max_divider = OMAP4430_MAX_DPLL_DIV,
|
|
|
+ .max_multiplier = 2047,
|
|
|
+ .max_divider = 128,
|
|
|
.min_divider = 1,
|
|
|
};
|
|
|
|
|
@@ -278,10 +278,10 @@ static struct clk dpll_abe_ck = {
|
|
|
static struct clk dpll_abe_x2_ck = {
|
|
|
.name = "dpll_abe_x2_ck",
|
|
|
.parent = &dpll_abe_ck,
|
|
|
+ .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE,
|
|
|
.flags = CLOCK_CLKOUTX2,
|
|
|
.ops = &clkops_omap4_dpllmx_ops,
|
|
|
.recalc = &omap3_clkoutx2_recalc,
|
|
|
- .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE,
|
|
|
};
|
|
|
|
|
|
static const struct clksel_rate div31_1to31_rates[] = {
|
|
@@ -434,8 +434,8 @@ static struct dpll_data dpll_core_dd = {
|
|
|
.enable_mask = OMAP4430_DPLL_EN_MASK,
|
|
|
.autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
|
|
|
.idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
|
|
|
- .max_multiplier = OMAP4430_MAX_DPLL_MULT,
|
|
|
- .max_divider = OMAP4430_MAX_DPLL_DIV,
|
|
|
+ .max_multiplier = 2047,
|
|
|
+ .max_divider = 128,
|
|
|
.min_divider = 1,
|
|
|
};
|
|
|
|
|
@@ -622,11 +622,11 @@ static struct clk dpll_core_m3x2_ck = {
|
|
|
.clksel_reg = OMAP4430_CM_DIV_M3_DPLL_CORE,
|
|
|
.clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
|
|
|
.ops = &clkops_omap2_dflt,
|
|
|
- .enable_reg = OMAP4430_CM_DIV_M3_DPLL_CORE,
|
|
|
- .enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
|
|
|
.recalc = &omap2_clksel_recalc,
|
|
|
.round_rate = &omap2_clksel_round_rate,
|
|
|
.set_rate = &omap2_clksel_set_rate,
|
|
|
+ .enable_reg = OMAP4430_CM_DIV_M3_DPLL_CORE,
|
|
|
+ .enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
|
|
|
};
|
|
|
|
|
|
static struct clk dpll_core_m7x2_ck = {
|
|
@@ -672,8 +672,8 @@ static struct dpll_data dpll_iva_dd = {
|
|
|
.enable_mask = OMAP4430_DPLL_EN_MASK,
|
|
|
.autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
|
|
|
.idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
|
|
|
- .max_multiplier = OMAP4430_MAX_DPLL_MULT,
|
|
|
- .max_divider = OMAP4430_MAX_DPLL_DIV,
|
|
|
+ .max_multiplier = 2047,
|
|
|
+ .max_divider = 128,
|
|
|
.min_divider = 1,
|
|
|
};
|
|
|
|
|
@@ -740,8 +740,8 @@ static struct dpll_data dpll_mpu_dd = {
|
|
|
.enable_mask = OMAP4430_DPLL_EN_MASK,
|
|
|
.autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
|
|
|
.idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
|
|
|
- .max_multiplier = OMAP4430_MAX_DPLL_MULT,
|
|
|
- .max_divider = OMAP4430_MAX_DPLL_DIV,
|
|
|
+ .max_multiplier = 2047,
|
|
|
+ .max_divider = 128,
|
|
|
.min_divider = 1,
|
|
|
};
|
|
|
|
|
@@ -813,8 +813,8 @@ static struct dpll_data dpll_per_dd = {
|
|
|
.enable_mask = OMAP4430_DPLL_EN_MASK,
|
|
|
.autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
|
|
|
.idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
|
|
|
- .max_multiplier = OMAP4430_MAX_DPLL_MULT,
|
|
|
- .max_divider = OMAP4430_MAX_DPLL_DIV,
|
|
|
+ .max_multiplier = 2047,
|
|
|
+ .max_divider = 128,
|
|
|
.min_divider = 1,
|
|
|
};
|
|
|
|
|
@@ -850,10 +850,10 @@ static struct clk dpll_per_m2_ck = {
|
|
|
static struct clk dpll_per_x2_ck = {
|
|
|
.name = "dpll_per_x2_ck",
|
|
|
.parent = &dpll_per_ck,
|
|
|
+ .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER,
|
|
|
.flags = CLOCK_CLKOUTX2,
|
|
|
.ops = &clkops_omap4_dpllmx_ops,
|
|
|
.recalc = &omap3_clkoutx2_recalc,
|
|
|
- .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER,
|
|
|
};
|
|
|
|
|
|
static const struct clksel dpll_per_m2x2_div[] = {
|
|
@@ -880,11 +880,11 @@ static struct clk dpll_per_m3x2_ck = {
|
|
|
.clksel_reg = OMAP4430_CM_DIV_M3_DPLL_PER,
|
|
|
.clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
|
|
|
.ops = &clkops_omap2_dflt,
|
|
|
- .enable_reg = OMAP4430_CM_DIV_M3_DPLL_PER,
|
|
|
- .enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
|
|
|
.recalc = &omap2_clksel_recalc,
|
|
|
.round_rate = &omap2_clksel_round_rate,
|
|
|
.set_rate = &omap2_clksel_set_rate,
|
|
|
+ .enable_reg = OMAP4430_CM_DIV_M3_DPLL_PER,
|
|
|
+ .enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
|
|
|
};
|
|
|
|
|
|
static struct clk dpll_per_m4x2_ck = {
|
|
@@ -935,63 +935,6 @@ static struct clk dpll_per_m7x2_ck = {
|
|
|
.set_rate = &omap2_clksel_set_rate,
|
|
|
};
|
|
|
|
|
|
-/* DPLL_UNIPRO */
|
|
|
-static struct dpll_data dpll_unipro_dd = {
|
|
|
- .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_UNIPRO,
|
|
|
- .clk_bypass = &sys_clkin_ck,
|
|
|
- .clk_ref = &sys_clkin_ck,
|
|
|
- .control_reg = OMAP4430_CM_CLKMODE_DPLL_UNIPRO,
|
|
|
- .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
|
|
|
- .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO,
|
|
|
- .idlest_reg = OMAP4430_CM_IDLEST_DPLL_UNIPRO,
|
|
|
- .mult_mask = OMAP4430_DPLL_MULT_MASK,
|
|
|
- .div1_mask = OMAP4430_DPLL_DIV_MASK,
|
|
|
- .enable_mask = OMAP4430_DPLL_EN_MASK,
|
|
|
- .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
|
|
|
- .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
|
|
|
- .sddiv_mask = OMAP4430_DPLL_SD_DIV_MASK,
|
|
|
- .max_multiplier = OMAP4430_MAX_DPLL_MULT,
|
|
|
- .max_divider = OMAP4430_MAX_DPLL_DIV,
|
|
|
- .min_divider = 1,
|
|
|
-};
|
|
|
-
|
|
|
-
|
|
|
-static struct clk dpll_unipro_ck = {
|
|
|
- .name = "dpll_unipro_ck",
|
|
|
- .parent = &sys_clkin_ck,
|
|
|
- .dpll_data = &dpll_unipro_dd,
|
|
|
- .init = &omap2_init_dpll_parent,
|
|
|
- .ops = &clkops_omap3_noncore_dpll_ops,
|
|
|
- .recalc = &omap3_dpll_recalc,
|
|
|
- .round_rate = &omap2_dpll_round_rate,
|
|
|
- .set_rate = &omap3_noncore_dpll_set_rate,
|
|
|
-};
|
|
|
-
|
|
|
-static struct clk dpll_unipro_x2_ck = {
|
|
|
- .name = "dpll_unipro_x2_ck",
|
|
|
- .parent = &dpll_unipro_ck,
|
|
|
- .flags = CLOCK_CLKOUTX2,
|
|
|
- .ops = &clkops_null,
|
|
|
- .recalc = &omap3_clkoutx2_recalc,
|
|
|
-};
|
|
|
-
|
|
|
-static const struct clksel dpll_unipro_m2x2_div[] = {
|
|
|
- { .parent = &dpll_unipro_x2_ck, .rates = div31_1to31_rates },
|
|
|
- { .parent = NULL },
|
|
|
-};
|
|
|
-
|
|
|
-static struct clk dpll_unipro_m2x2_ck = {
|
|
|
- .name = "dpll_unipro_m2x2_ck",
|
|
|
- .parent = &dpll_unipro_x2_ck,
|
|
|
- .clksel = dpll_unipro_m2x2_div,
|
|
|
- .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_UNIPRO,
|
|
|
- .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
|
|
|
- .ops = &clkops_omap4_dpllmx_ops,
|
|
|
- .recalc = &omap2_clksel_recalc,
|
|
|
- .round_rate = &omap2_clksel_round_rate,
|
|
|
- .set_rate = &omap2_clksel_set_rate,
|
|
|
-};
|
|
|
-
|
|
|
static struct clk usb_hs_clk_div_ck = {
|
|
|
.name = "usb_hs_clk_div_ck",
|
|
|
.parent = &dpll_abe_m3x2_ck,
|
|
@@ -1015,8 +958,9 @@ static struct dpll_data dpll_usb_dd = {
|
|
|
.enable_mask = OMAP4430_DPLL_EN_MASK,
|
|
|
.autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
|
|
|
.idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
|
|
|
- .max_multiplier = OMAP4430_MAX_DPLL_MULT,
|
|
|
- .max_divider = OMAP4430_MAX_DPLL_DIV,
|
|
|
+ .sddiv_mask = OMAP4430_DPLL_SD_DIV_MASK,
|
|
|
+ .max_multiplier = 4095,
|
|
|
+ .max_divider = 256,
|
|
|
.min_divider = 1,
|
|
|
};
|
|
|
|
|
@@ -1035,8 +979,8 @@ static struct clk dpll_usb_ck = {
|
|
|
static struct clk dpll_usb_clkdcoldo_ck = {
|
|
|
.name = "dpll_usb_clkdcoldo_ck",
|
|
|
.parent = &dpll_usb_ck,
|
|
|
- .ops = &clkops_omap4_dpllmx_ops,
|
|
|
.clksel_reg = OMAP4430_CM_CLKDCOLDO_DPLL_USB,
|
|
|
+ .ops = &clkops_omap4_dpllmx_ops,
|
|
|
.recalc = &followparent_recalc,
|
|
|
};
|
|
|
|
|
@@ -1169,19 +1113,6 @@ static struct clk func_96m_fclk = {
|
|
|
.set_rate = &omap2_clksel_set_rate,
|
|
|
};
|
|
|
|
|
|
-static const struct clksel hsmmc6_fclk_sel[] = {
|
|
|
- { .parent = &func_64m_fclk, .rates = div_1_0_rates },
|
|
|
- { .parent = &func_96m_fclk, .rates = div_1_1_rates },
|
|
|
- { .parent = NULL },
|
|
|
-};
|
|
|
-
|
|
|
-static struct clk hsmmc6_fclk = {
|
|
|
- .name = "hsmmc6_fclk",
|
|
|
- .parent = &func_64m_fclk,
|
|
|
- .ops = &clkops_null,
|
|
|
- .recalc = &followparent_recalc,
|
|
|
-};
|
|
|
-
|
|
|
static const struct clksel_rate div2_1to8_rates[] = {
|
|
|
{ .div = 1, .val = 0, .flags = RATE_IN_4430 },
|
|
|
{ .div = 8, .val = 1, .flags = RATE_IN_4430 },
|
|
@@ -1264,6 +1195,21 @@ static struct clk l4_wkup_clk_mux_ck = {
|
|
|
.recalc = &omap2_clksel_recalc,
|
|
|
};
|
|
|
|
|
|
+static struct clk ocp_abe_iclk = {
|
|
|
+ .name = "ocp_abe_iclk",
|
|
|
+ .parent = &aess_fclk,
|
|
|
+ .ops = &clkops_null,
|
|
|
+ .recalc = &followparent_recalc,
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk per_abe_24m_fclk = {
|
|
|
+ .name = "per_abe_24m_fclk",
|
|
|
+ .parent = &dpll_abe_m2_ck,
|
|
|
+ .ops = &clkops_null,
|
|
|
+ .fixed_div = 4,
|
|
|
+ .recalc = &omap_fixed_divisor_recalc,
|
|
|
+};
|
|
|
+
|
|
|
static const struct clksel per_abe_nc_fclk_div[] = {
|
|
|
{ .parent = &dpll_abe_m2_ck, .rates = div2_1to2_rates },
|
|
|
{ .parent = NULL },
|
|
@@ -1281,41 +1227,6 @@ static struct clk per_abe_nc_fclk = {
|
|
|
.set_rate = &omap2_clksel_set_rate,
|
|
|
};
|
|
|
|
|
|
-static const struct clksel mcasp2_fclk_sel[] = {
|
|
|
- { .parent = &func_96m_fclk, .rates = div_1_0_rates },
|
|
|
- { .parent = &per_abe_nc_fclk, .rates = div_1_1_rates },
|
|
|
- { .parent = NULL },
|
|
|
-};
|
|
|
-
|
|
|
-static struct clk mcasp2_fclk = {
|
|
|
- .name = "mcasp2_fclk",
|
|
|
- .parent = &func_96m_fclk,
|
|
|
- .ops = &clkops_null,
|
|
|
- .recalc = &followparent_recalc,
|
|
|
-};
|
|
|
-
|
|
|
-static struct clk mcasp3_fclk = {
|
|
|
- .name = "mcasp3_fclk",
|
|
|
- .parent = &func_96m_fclk,
|
|
|
- .ops = &clkops_null,
|
|
|
- .recalc = &followparent_recalc,
|
|
|
-};
|
|
|
-
|
|
|
-static struct clk ocp_abe_iclk = {
|
|
|
- .name = "ocp_abe_iclk",
|
|
|
- .parent = &aess_fclk,
|
|
|
- .ops = &clkops_null,
|
|
|
- .recalc = &followparent_recalc,
|
|
|
-};
|
|
|
-
|
|
|
-static struct clk per_abe_24m_fclk = {
|
|
|
- .name = "per_abe_24m_fclk",
|
|
|
- .parent = &dpll_abe_m2_ck,
|
|
|
- .ops = &clkops_null,
|
|
|
- .fixed_div = 4,
|
|
|
- .recalc = &omap_fixed_divisor_recalc,
|
|
|
-};
|
|
|
-
|
|
|
static const struct clksel pmd_stm_clock_mux_sel[] = {
|
|
|
{ .parent = &sys_clkin_ck, .rates = div_1_0_rates },
|
|
|
{ .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates },
|
|
@@ -1846,8 +1757,8 @@ static struct clk l3_instr_ick = {
|
|
|
.ops = &clkops_omap2_dflt,
|
|
|
.enable_reg = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL,
|
|
|
.enable_bit = OMAP4430_MODULEMODE_HWCTRL,
|
|
|
- .clkdm_name = "l3_instr_clkdm",
|
|
|
.flags = ENABLE_ON_INIT,
|
|
|
+ .clkdm_name = "l3_instr_clkdm",
|
|
|
.parent = &l3_div_ck,
|
|
|
.recalc = &followparent_recalc,
|
|
|
};
|
|
@@ -1857,8 +1768,8 @@ static struct clk l3_main_3_ick = {
|
|
|
.ops = &clkops_omap2_dflt,
|
|
|
.enable_reg = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL,
|
|
|
.enable_bit = OMAP4430_MODULEMODE_HWCTRL,
|
|
|
- .clkdm_name = "l3_instr_clkdm",
|
|
|
.flags = ENABLE_ON_INIT,
|
|
|
+ .clkdm_name = "l3_instr_clkdm",
|
|
|
.parent = &l3_div_ck,
|
|
|
.recalc = &followparent_recalc,
|
|
|
};
|
|
@@ -1995,10 +1906,16 @@ static struct clk mcbsp3_fck = {
|
|
|
.clkdm_name = "abe_clkdm",
|
|
|
};
|
|
|
|
|
|
+static const struct clksel mcbsp4_sync_mux_sel[] = {
|
|
|
+ { .parent = &func_96m_fclk, .rates = div_1_0_rates },
|
|
|
+ { .parent = &per_abe_nc_fclk, .rates = div_1_1_rates },
|
|
|
+ { .parent = NULL },
|
|
|
+};
|
|
|
+
|
|
|
static struct clk mcbsp4_sync_mux_ck = {
|
|
|
.name = "mcbsp4_sync_mux_ck",
|
|
|
.parent = &func_96m_fclk,
|
|
|
- .clksel = mcasp2_fclk_sel,
|
|
|
+ .clksel = mcbsp4_sync_mux_sel,
|
|
|
.init = &omap2_init_clksel_parent,
|
|
|
.clksel_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
|
|
|
.clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
|
|
@@ -2077,11 +1994,17 @@ static struct clk mcspi4_fck = {
|
|
|
.recalc = &followparent_recalc,
|
|
|
};
|
|
|
|
|
|
+static const struct clksel hsmmc1_fclk_sel[] = {
|
|
|
+ { .parent = &func_64m_fclk, .rates = div_1_0_rates },
|
|
|
+ { .parent = &func_96m_fclk, .rates = div_1_1_rates },
|
|
|
+ { .parent = NULL },
|
|
|
+};
|
|
|
+
|
|
|
/* Merged hsmmc1_fclk into mmc1 */
|
|
|
static struct clk mmc1_fck = {
|
|
|
.name = "mmc1_fck",
|
|
|
.parent = &func_64m_fclk,
|
|
|
- .clksel = hsmmc6_fclk_sel,
|
|
|
+ .clksel = hsmmc1_fclk_sel,
|
|
|
.init = &omap2_init_clksel_parent,
|
|
|
.clksel_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
|
|
|
.clksel_mask = OMAP4430_CLKSEL_MASK,
|
|
@@ -2096,7 +2019,7 @@ static struct clk mmc1_fck = {
|
|
|
static struct clk mmc2_fck = {
|
|
|
.name = "mmc2_fck",
|
|
|
.parent = &func_64m_fclk,
|
|
|
- .clksel = hsmmc6_fclk_sel,
|
|
|
+ .clksel = hsmmc1_fclk_sel,
|
|
|
.init = &omap2_init_clksel_parent,
|
|
|
.clksel_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
|
|
|
.clksel_mask = OMAP4430_CLKSEL_MASK,
|
|
@@ -2162,8 +2085,8 @@ static struct clk ocp_wp_noc_ick = {
|
|
|
.ops = &clkops_omap2_dflt,
|
|
|
.enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL,
|
|
|
.enable_bit = OMAP4430_MODULEMODE_HWCTRL,
|
|
|
- .clkdm_name = "l3_instr_clkdm",
|
|
|
.flags = ENABLE_ON_INIT,
|
|
|
+ .clkdm_name = "l3_instr_clkdm",
|
|
|
.parent = &l3_div_ck,
|
|
|
.recalc = &followparent_recalc,
|
|
|
};
|
|
@@ -2895,6 +2818,7 @@ static struct clk auxclk2_ck = {
|
|
|
.enable_reg = OMAP4_SCRM_AUXCLK2,
|
|
|
.enable_bit = OMAP4_ENABLE_SHIFT,
|
|
|
};
|
|
|
+
|
|
|
static struct clk auxclk3_ck = {
|
|
|
.name = "auxclk3_ck",
|
|
|
.parent = &sys_clkin_ck,
|
|
@@ -3077,9 +3001,6 @@ static struct omap_clk omap44xx_clks[] = {
|
|
|
CLK(NULL, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, CK_443X),
|
|
|
CLK(NULL, "dpll_per_m6x2_ck", &dpll_per_m6x2_ck, CK_443X),
|
|
|
CLK(NULL, "dpll_per_m7x2_ck", &dpll_per_m7x2_ck, CK_443X),
|
|
|
- CLK(NULL, "dpll_unipro_ck", &dpll_unipro_ck, CK_443X),
|
|
|
- CLK(NULL, "dpll_unipro_x2_ck", &dpll_unipro_x2_ck, CK_443X),
|
|
|
- CLK(NULL, "dpll_unipro_m2x2_ck", &dpll_unipro_m2x2_ck, CK_443X),
|
|
|
CLK(NULL, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck, CK_443X),
|
|
|
CLK(NULL, "dpll_usb_ck", &dpll_usb_ck, CK_443X),
|
|
|
CLK(NULL, "dpll_usb_clkdcoldo_ck", &dpll_usb_clkdcoldo_ck, CK_443X),
|
|
@@ -3092,17 +3013,14 @@ static struct omap_clk omap44xx_clks[] = {
|
|
|
CLK(NULL, "func_48mc_fclk", &func_48mc_fclk, CK_443X),
|
|
|
CLK(NULL, "func_64m_fclk", &func_64m_fclk, CK_443X),
|
|
|
CLK(NULL, "func_96m_fclk", &func_96m_fclk, CK_443X),
|
|
|
- CLK(NULL, "hsmmc6_fclk", &hsmmc6_fclk, CK_443X),
|
|
|
CLK(NULL, "init_60m_fclk", &init_60m_fclk, CK_443X),
|
|
|
CLK(NULL, "l3_div_ck", &l3_div_ck, CK_443X),
|
|
|
CLK(NULL, "l4_div_ck", &l4_div_ck, CK_443X),
|
|
|
CLK(NULL, "lp_clk_div_ck", &lp_clk_div_ck, CK_443X),
|
|
|
CLK(NULL, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, CK_443X),
|
|
|
- CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk, CK_443X),
|
|
|
- CLK(NULL, "mcasp2_fclk", &mcasp2_fclk, CK_443X),
|
|
|
- CLK(NULL, "mcasp3_fclk", &mcasp3_fclk, CK_443X),
|
|
|
CLK(NULL, "ocp_abe_iclk", &ocp_abe_iclk, CK_443X),
|
|
|
CLK(NULL, "per_abe_24m_fclk", &per_abe_24m_fclk, CK_443X),
|
|
|
+ CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk, CK_443X),
|
|
|
CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck, CK_443X),
|
|
|
CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck, CK_443X),
|
|
|
CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck, CK_443X),
|
|
@@ -3204,7 +3122,6 @@ static struct omap_clk omap44xx_clks[] = {
|
|
|
CLK(NULL, "uart2_fck", &uart2_fck, CK_443X),
|
|
|
CLK(NULL, "uart3_fck", &uart3_fck, CK_443X),
|
|
|
CLK(NULL, "uart4_fck", &uart4_fck, CK_443X),
|
|
|
- CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X),
|
|
|
CLK("usbhs-omap.0", "fs_fck", &usb_host_fs_fck, CK_443X),
|
|
|
CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X),
|
|
|
CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk, CK_443X),
|
|
@@ -3216,9 +3133,7 @@ static struct omap_clk omap44xx_clks[] = {
|
|
|
CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk, CK_443X),
|
|
|
CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk, CK_443X),
|
|
|
CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk, CK_443X),
|
|
|
- CLK(NULL, "usb_host_hs_fck", &usb_host_hs_fck, CK_443X),
|
|
|
CLK("usbhs-omap.0", "hs_fck", &usb_host_hs_fck, CK_443X),
|
|
|
- CLK("usbhs-omap.0", "usbhost_ick", &dummy_ck, CK_443X),
|
|
|
CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk, CK_443X),
|
|
|
CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk, CK_443X),
|
|
|
CLK("musb-omap2430", "ick", &usb_otg_hs_ick, CK_443X),
|
|
@@ -3226,17 +3141,26 @@ static struct omap_clk omap44xx_clks[] = {
|
|
|
CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk, CK_443X),
|
|
|
CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk, CK_443X),
|
|
|
CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk, CK_443X),
|
|
|
- CLK(NULL, "usb_tll_hs_ick", &usb_tll_hs_ick, CK_443X),
|
|
|
CLK("usbhs-omap.0", "usbtll_ick", &usb_tll_hs_ick, CK_443X),
|
|
|
- CLK("usbhs-omap.0", "usbtll_fck", &dummy_ck, CK_443X),
|
|
|
CLK(NULL, "usim_ck", &usim_ck, CK_443X),
|
|
|
CLK(NULL, "usim_fclk", &usim_fclk, CK_443X),
|
|
|
CLK(NULL, "usim_fck", &usim_fck, CK_443X),
|
|
|
CLK("omap_wdt", "fck", &wd_timer2_fck, CK_443X),
|
|
|
- CLK(NULL, "mailboxes_ick", &dummy_ck, CK_443X),
|
|
|
CLK(NULL, "wd_timer3_fck", &wd_timer3_fck, CK_443X),
|
|
|
CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X),
|
|
|
CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X),
|
|
|
+ CLK(NULL, "auxclk0_ck", &auxclk0_ck, CK_443X),
|
|
|
+ CLK(NULL, "auxclk1_ck", &auxclk1_ck, CK_443X),
|
|
|
+ CLK(NULL, "auxclk2_ck", &auxclk2_ck, CK_443X),
|
|
|
+ CLK(NULL, "auxclk3_ck", &auxclk3_ck, CK_443X),
|
|
|
+ CLK(NULL, "auxclk4_ck", &auxclk4_ck, CK_443X),
|
|
|
+ CLK(NULL, "auxclk5_ck", &auxclk5_ck, CK_443X),
|
|
|
+ CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck, CK_443X),
|
|
|
+ CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck, CK_443X),
|
|
|
+ CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck, CK_443X),
|
|
|
+ CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck, CK_443X),
|
|
|
+ CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck, CK_443X),
|
|
|
+ CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck, CK_443X),
|
|
|
CLK(NULL, "gpmc_ck", &dummy_ck, CK_443X),
|
|
|
CLK(NULL, "gpt1_ick", &dummy_ck, CK_443X),
|
|
|
CLK(NULL, "gpt2_ick", &dummy_ck, CK_443X),
|
|
@@ -3253,6 +3177,7 @@ static struct omap_clk omap44xx_clks[] = {
|
|
|
CLK("omap_i2c.2", "ick", &dummy_ck, CK_443X),
|
|
|
CLK("omap_i2c.3", "ick", &dummy_ck, CK_443X),
|
|
|
CLK("omap_i2c.4", "ick", &dummy_ck, CK_443X),
|
|
|
+ CLK(NULL, "mailboxes_ick", &dummy_ck, CK_443X),
|
|
|
CLK("omap_hsmmc.0", "ick", &dummy_ck, CK_443X),
|
|
|
CLK("omap_hsmmc.1", "ick", &dummy_ck, CK_443X),
|
|
|
CLK("omap_hsmmc.2", "ick", &dummy_ck, CK_443X),
|
|
@@ -3270,19 +3195,9 @@ static struct omap_clk omap44xx_clks[] = {
|
|
|
CLK(NULL, "uart2_ick", &dummy_ck, CK_443X),
|
|
|
CLK(NULL, "uart3_ick", &dummy_ck, CK_443X),
|
|
|
CLK(NULL, "uart4_ick", &dummy_ck, CK_443X),
|
|
|
+ CLK("usbhs-omap.0", "usbhost_ick", &dummy_ck, CK_443X),
|
|
|
+ CLK("usbhs-omap.0", "usbtll_fck", &dummy_ck, CK_443X),
|
|
|
CLK("omap_wdt", "ick", &dummy_ck, CK_443X),
|
|
|
- CLK(NULL, "auxclk0_ck", &auxclk0_ck, CK_443X),
|
|
|
- CLK(NULL, "auxclk1_ck", &auxclk1_ck, CK_443X),
|
|
|
- CLK(NULL, "auxclk2_ck", &auxclk2_ck, CK_443X),
|
|
|
- CLK(NULL, "auxclk3_ck", &auxclk3_ck, CK_443X),
|
|
|
- CLK(NULL, "auxclk4_ck", &auxclk4_ck, CK_443X),
|
|
|
- CLK(NULL, "auxclk5_ck", &auxclk5_ck, CK_443X),
|
|
|
- CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck, CK_443X),
|
|
|
- CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck, CK_443X),
|
|
|
- CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck, CK_443X),
|
|
|
- CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck, CK_443X),
|
|
|
- CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck, CK_443X),
|
|
|
- CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck, CK_443X),
|
|
|
};
|
|
|
|
|
|
int __init omap4xxx_clk_init(void)
|