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@@ -5076,6 +5076,34 @@ static void i9xx_get_pfit_config(struct intel_crtc *crtc,
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I915_READ(LVDS) & LVDS_BORDER_ENABLE;
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}
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+static void vlv_crtc_clock_get(struct intel_crtc *crtc,
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+ struct intel_crtc_config *pipe_config)
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+{
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+ struct drm_device *dev = crtc->base.dev;
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+ struct drm_i915_private *dev_priv = dev->dev_private;
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+ int pipe = pipe_config->cpu_transcoder;
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+ intel_clock_t clock;
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+ u32 mdiv;
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+ int refclk = 100000, fastclk, update_rate;
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+
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+ mutex_lock(&dev_priv->dpio_lock);
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+ mdiv = vlv_dpio_read(dev_priv, pipe, DPIO_DIV(pipe));
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+ mutex_unlock(&dev_priv->dpio_lock);
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+
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+ clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
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+ clock.m2 = mdiv & DPIO_M2DIV_MASK;
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+ clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
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+ clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
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+ clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
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+
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+ update_rate = refclk / clock.n;
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+ clock.vco = update_rate * clock.m1 * clock.m2;
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+ fastclk = clock.vco / clock.p1 / clock.p2;
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+ clock.dot = (2 * fastclk);
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+
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+ pipe_config->port_clock = clock.dot / 10;
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+}
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+
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static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
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struct intel_crtc_config *pipe_config)
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{
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@@ -5141,7 +5169,10 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
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DPLL_PORTB_READY_MASK);
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}
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- i9xx_crtc_clock_get(crtc, pipe_config);
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+ if (IS_VALLEYVIEW(dev))
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+ vlv_crtc_clock_get(crtc, pipe_config);
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+ else
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+ i9xx_crtc_clock_get(crtc, pipe_config);
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return true;
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}
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