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@@ -308,7 +308,6 @@ static int omap1_select_table_rate(struct clk * clk, unsigned long rate)
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omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val);
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ck_dpll1.rate = ptr->pll_rate;
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- propagate_rate(&ck_dpll1);
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return 0;
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}
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@@ -333,9 +332,6 @@ static int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate)
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ret = 0;
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}
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- if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES)))
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- propagate_rate(clk);
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-
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return ret;
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}
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@@ -442,8 +438,6 @@ static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate)
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omap_writel(l, MOD_CONF_CTRL_1);
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clk->rate = p_rate / (div + 1);
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- if (unlikely(clk->flags & RATE_PROPAGATES))
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- propagate_rate(clk);
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return 0;
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}
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@@ -787,7 +781,6 @@ int __init omap1_clk_init(void)
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}
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}
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}
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- propagate_rate(&ck_dpll1);
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#else
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/* Find the highest supported frequency and enable it */
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if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) {
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@@ -796,9 +789,9 @@ int __init omap1_clk_init(void)
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omap_writew(0x2290, DPLL_CTL);
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omap_writew(cpu_is_omap730() ? 0x3005 : 0x1005, ARM_CKCTL);
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ck_dpll1.rate = 60000000;
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- propagate_rate(&ck_dpll1);
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}
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#endif
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+ propagate_rate(&ck_dpll1);
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/* Cache rates for clocks connected to ck_ref (not dpll1) */
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propagate_rate(&ck_ref);
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printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): "
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