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@@ -42,6 +42,7 @@
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#define WL18XX_RX_CHECKSUM_MASK 0x40
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static char *ht_mode_param;
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+static char *board_type_param;
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static const u8 wl18xx_rate_to_idx_2ghz[] = {
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/* MCS rates are used only with 11n */
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@@ -680,8 +681,7 @@ static void wl18xx_set_mac_and_phy(struct wl1271 *wl)
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params.secondary_clock_setting_time =
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phy->secondary_clock_setting_time;
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- /* TODO: hardcoded for now */
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- params.board_type = BOARD_TYPE_DVP_EVB_18XX;
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+ params.board_type = priv->board_type;
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wlcore_set_partition(wl, &wl->ptable[PART_PHY_INIT]);
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wl1271_write(wl, WL18XX_PHY_INIT_MEM_ADDR, (u8 *)¶ms,
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@@ -964,6 +964,7 @@ int __devinit wl18xx_probe(struct platform_device *pdev)
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}
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wl = hw->priv;
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+ priv = wl->priv;
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wl->ops = &wl18xx_ops;
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wl->ptable = wl18xx_ptable;
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wl->rtable = wl18xx_rtable;
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@@ -979,6 +980,24 @@ int __devinit wl18xx_probe(struct platform_device *pdev)
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memcpy(&wl->ht_cap, &wl18xx_mimo_ht_cap,
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sizeof(wl18xx_mimo_ht_cap));
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+ if (!board_type_param) {
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+ board_type_param = kstrdup("dvp_evb", GFP_KERNEL);
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+ priv->board_type = BOARD_TYPE_DVP_EVB_18XX;
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+ } else {
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+ if (!strcmp(board_type_param, "fpga"))
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+ priv->board_type = BOARD_TYPE_FPGA_18XX;
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+ else if (!strcmp(board_type_param, "hdk"))
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+ priv->board_type = BOARD_TYPE_HDK_18XX;
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+ else if (!strcmp(board_type_param, "dvp_evb"))
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+ priv->board_type = BOARD_TYPE_DVP_EVB_18XX;
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+ else {
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+ wl1271_error("invalid board type '%s'",
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+ board_type_param);
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+ wlcore_free_hw(wl);
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+ return -EINVAL;
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+ }
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+ }
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+
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wl18xx_conf_init(wl);
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return wlcore_probe(wl, pdev);
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@@ -1015,6 +1034,9 @@ module_exit(wl18xx_exit);
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module_param_named(ht_mode, ht_mode_param, charp, S_IRUSR);
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MODULE_PARM_DESC(ht_mode, "Force HT mode: wide or mimo");
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+module_param_named(board_type, board_type_param, charp, S_IRUSR);
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+MODULE_PARM_DESC(board_type, "Board type: fpga, hdk or dvp_evb (default)");
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+
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MODULE_LICENSE("GPL v2");
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MODULE_AUTHOR("Luciano Coelho <coelho@ti.com>");
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MODULE_FIRMWARE(WL18XX_FW_NAME);
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