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@@ -150,24 +150,6 @@ static struct clksrc_clk clk_periphclk = {
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.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 },
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};
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-static struct clksrc_clk clk_atclk = {
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- .clk = {
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- .name = "atclk",
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- .id = -1,
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- .parent = &clk_moutcore.clk,
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- },
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- .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 16, .size = 3 },
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-};
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-
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-static struct clksrc_clk clk_pclk_dbg = {
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- .clk = {
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- .name = "pclk_dbg",
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- .id = -1,
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- .parent = &clk_atclk.clk,
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- },
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- .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 20, .size = 3 },
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-};
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-
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/* Core list of CMU_CORE side */
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static struct clk *clkset_corebus_list[] = {
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@@ -464,8 +446,6 @@ static struct clksrc_clk *sysclks[] = {
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&clk_aclk_cores,
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&clk_aclk_corem1,
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&clk_periphclk,
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- &clk_atclk,
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- &clk_pclk_dbg,
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&clk_mout_corebus,
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&clk_sclk_dmc,
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&clk_aclk_cored,
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@@ -490,15 +470,7 @@ void __init_or_cpufreq s5pv310_setup_clocks(void)
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unsigned long vpllsrc;
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unsigned long xtal;
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unsigned long armclk;
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- unsigned long aclk_corem0;
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- unsigned long aclk_cores;
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- unsigned long aclk_corem1;
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- unsigned long periphclk;
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unsigned long sclk_dmc;
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- unsigned long aclk_cored;
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- unsigned long aclk_corep;
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- unsigned long aclk_acp;
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- unsigned long pclk_acp;
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unsigned int ptr;
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printk(KERN_DEBUG "%s: registering clocks\n", __func__);
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@@ -529,26 +501,12 @@ void __init_or_cpufreq s5pv310_setup_clocks(void)
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apll, mpll, epll, vpll);
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armclk = clk_get_rate(&clk_armclk.clk);
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- aclk_corem0 = clk_get_rate(&clk_aclk_corem0.clk);
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- aclk_cores = clk_get_rate(&clk_aclk_cores.clk);
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- aclk_corem1 = clk_get_rate(&clk_aclk_corem1.clk);
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- periphclk = clk_get_rate(&clk_periphclk.clk);
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sclk_dmc = clk_get_rate(&clk_sclk_dmc.clk);
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- aclk_cored = clk_get_rate(&clk_aclk_cored.clk);
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- aclk_corep = clk_get_rate(&clk_aclk_corep.clk);
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- aclk_acp = clk_get_rate(&clk_aclk_acp.clk);
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- pclk_acp = clk_get_rate(&clk_pclk_acp.clk);
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-
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- printk(KERN_INFO "S5PV310: ARMCLK=%ld, COREM0=%ld, CORES=%ld\n"
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- "COREM1=%ld, PERI=%ld, DMC=%ld, CORED=%ld\n"
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- "COREP=%ld, ACLK_ACP=%ld, PCLK_ACP=%ld",
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- armclk, aclk_corem0, aclk_cores, aclk_corem1,
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- periphclk, sclk_dmc, aclk_cored, aclk_corep,
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- aclk_acp, pclk_acp);
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+
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+ printk(KERN_INFO "S5PV310: ARMCLK=%ld, DMC=%ld\n", armclk, sclk_dmc);
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clk_f.rate = armclk;
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clk_h.rate = sclk_dmc;
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- clk_p.rate = periphclk;
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for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
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s3c_set_clksrc(&clksrcs[ptr], true);
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Kukjin Kim