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@@ -919,15 +919,15 @@ static void b43_nphy_gain_ctrl_workarounds(struct b43_wldev *dev)
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B43_NPHY_C2_CGAINI_CL2DETECT);
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/* Set narrowband clip threshold */
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- b43_phy_set(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84);
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- b43_phy_set(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84);
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+ b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84);
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+ b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84);
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if (!dev->phy.is_40mhz) {
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/* Set dwell lengths */
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- b43_phy_set(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
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- b43_phy_set(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
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- b43_phy_set(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
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- b43_phy_set(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
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+ b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
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+ b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
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+ b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
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+ b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
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}
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/* Set wideband clip 2 threshold */
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@@ -949,7 +949,7 @@ static void b43_nphy_gain_ctrl_workarounds(struct b43_wldev *dev)
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~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1);
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}
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- b43_phy_set(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
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+ b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
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if (nphy->gain_boost) {
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if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ &&
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@@ -970,10 +970,10 @@ static void b43_nphy_gain_ctrl_workarounds(struct b43_wldev *dev)
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code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
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b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
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- b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
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- (code << 8 | 0x7C));
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- b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
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- (code << 8 | 0x7C));
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+ /* specs say about 2 loops, but wl does 4 */
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+ for (i = 0; i < 4; i++)
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+ b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
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+ (code << 8 | 0x7C));
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b43_nphy_adjust_lna_gain_table(dev);
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@@ -991,10 +991,10 @@ static void b43_nphy_gain_ctrl_workarounds(struct b43_wldev *dev)
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b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
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b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
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- b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
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- (code << 8 | 0x74));
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- b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
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- (code << 8 | 0x74));
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+ /* specs say about 2 loops, but wl does 4 */
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+ for (i = 0; i < 4; i++)
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+ b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
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+ (code << 8 | 0x74));
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}
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if (dev->phy.rev == 2) {
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@@ -1034,7 +1034,7 @@ static void b43_nphy_workarounds(struct b43_wldev *dev)
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u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
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u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
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- if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
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+ if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
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b43_nphy_classifier(dev, 1, 0);
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else
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b43_nphy_classifier(dev, 1, 1);
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@@ -3459,7 +3459,8 @@ static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
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memset(nphy, 0, sizeof(*nphy));
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- //TODO init struct b43_phy_n
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+ /* wl goes path which is executed for gain_boost, assume it is true */
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+ nphy->gain_boost = true;
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}
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static void b43_nphy_op_free(struct b43_wldev *dev)
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