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@@ -30,6 +30,9 @@
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#define TIMER_CTL_REG(val) (0x10 * val + 0x10)
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#define TIMER_CTL_ENABLE BIT(0)
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#define TIMER_CTL_RELOAD BIT(1)
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+#define TIMER_CTL_CLK_SRC(val) (((val) & 0x3) << 2)
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+#define TIMER_CTL_CLK_SRC_OSC24M (1)
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+#define TIMER_CTL_CLK_PRES(val) (((val) & 0x7) << 4)
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#define TIMER_CTL_ONESHOT BIT(7)
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#define TIMER_INTVAL_REG(val) (0x10 * (val) + 0x14)
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#define TIMER_CNTVAL_REG(val) (0x10 * (val) + 0x18)
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@@ -168,16 +171,8 @@ static void __init sun4i_timer_init(struct device_node *node)
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writel(rate / HZ, timer_base + TIMER_INTVAL_REG(0));
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- /* set clock source to HOSC, 16 pre-division */
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- val = readl(timer_base + TIMER_CTL_REG(0));
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- val &= ~(0x07 << 4);
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- val &= ~(0x03 << 2);
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- val |= (4 << 4) | (1 << 2);
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- writel(val, timer_base + TIMER_CTL_REG(0));
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-
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- /* set mode to auto reload */
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- val = readl(timer_base + TIMER_CTL_REG(0));
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- writel(val | TIMER_CTL_RELOAD, timer_base + TIMER_CTL_REG(0));
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+ writel(TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M) | TIMER_CTL_RELOAD,
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+ timer_base + TIMER_CTL_REG(0));
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ret = setup_irq(irq, &sun4i_timer_irq);
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if (ret)
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