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@@ -38,17 +38,17 @@
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#include "rt_config.h"
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#include <linux/pci.h>
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-// Following information will be show when you run 'modinfo'
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-// *** If you have a solution for the bug in current version of driver, please mail to me.
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-// Otherwise post to forum in ralinktech's web site(www.ralinktech.com) and let all users help you. ***
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+/* Following information will be show when you run 'modinfo' */
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+/* *** If you have a solution for the bug in current version of driver, please mail to me. */
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+/* Otherwise post to forum in ralinktech's web site(www.ralinktech.com) and let all users help you. *** */
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MODULE_AUTHOR("Jett Chen <jett_chen@ralinktech.com>");
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MODULE_DESCRIPTION("RT2860/RT3090 Wireless Lan Linux Driver");
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MODULE_LICENSE("GPL");
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MODULE_ALIAS("rt3090sta");
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-//
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-// Function declarations
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-//
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+/* */
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+/* Function declarations */
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+/* */
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extern int rt28xx_close(IN struct net_device *net_dev);
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extern int rt28xx_open(struct net_device *net_dev);
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@@ -64,14 +64,14 @@ static VOID RTMPInitPCIeDevice(IN struct pci_dev *pci_dev,
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#ifdef CONFIG_PM
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static int rt2860_suspend(struct pci_dev *pci_dev, pm_message_t state);
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static int rt2860_resume(struct pci_dev *pci_dev);
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-#endif // CONFIG_PM //
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+#endif /* CONFIG_PM // */
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-//
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-// Ralink PCI device table, include all supported chipsets
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-//
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+/* */
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+/* Ralink PCI device table, include all supported chipsets */
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+/* */
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static struct pci_device_id rt2860_pci_tbl[] __devinitdata = {
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#ifdef RT2860
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- {PCI_DEVICE(NIC_PCI_VENDOR_ID, NIC2860_PCI_DEVICE_ID)}, //RT28602.4G
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+ {PCI_DEVICE(NIC_PCI_VENDOR_ID, NIC2860_PCI_DEVICE_ID)}, /*RT28602.4G */
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{PCI_DEVICE(NIC_PCI_VENDOR_ID, NIC2860_PCIe_DEVICE_ID)},
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{PCI_DEVICE(NIC_PCI_VENDOR_ID, NIC2760_PCI_DEVICE_ID)},
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{PCI_DEVICE(NIC_PCI_VENDOR_ID, NIC2790_PCIe_DEVICE_ID)},
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@@ -88,13 +88,13 @@ static struct pci_device_id rt2860_pci_tbl[] __devinitdata = {
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{PCI_DEVICE(NIC_PCI_VENDOR_ID, NIC3090_PCIe_DEVICE_ID)},
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{PCI_DEVICE(NIC_PCI_VENDOR_ID, NIC3091_PCIe_DEVICE_ID)},
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{PCI_DEVICE(NIC_PCI_VENDOR_ID, NIC3092_PCIe_DEVICE_ID)},
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-#endif // RT3090 //
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+#endif /* RT3090 // */
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#ifdef RT3390
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{PCI_DEVICE(NIC_PCI_VENDOR_ID, NIC3390_PCIe_DEVICE_ID)},
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{PCI_DEVICE(NIC_PCI_VENDOR_ID, NIC3391_PCIe_DEVICE_ID)},
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{PCI_DEVICE(NIC_PCI_VENDOR_ID, NIC3392_PCIe_DEVICE_ID)},
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-#endif // RT3390 //
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- {0,} // terminate list
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+#endif /* RT3390 // */
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+ {0,} /* terminate list */
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};
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MODULE_DEVICE_TABLE(pci, rt2860_pci_tbl);
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@@ -102,9 +102,9 @@ MODULE_DEVICE_TABLE(pci, rt2860_pci_tbl);
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MODULE_VERSION(STA_DRIVER_VERSION);
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#endif
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-//
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-// Our PCI driver structure
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-//
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+/* */
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+/* Our PCI driver structure */
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+/* */
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static struct pci_driver rt2860_driver = {
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name: "rt2860",
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id_table:rt2860_pci_tbl,
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@@ -125,8 +125,8 @@ resume:rt2860_resume,
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VOID RT2860RejectPendingPackets(IN PRTMP_ADAPTER pAd)
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{
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- // clear PS packets
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- // clear TxSw packets
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+ /* clear PS packets */
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+ /* clear TxSw packets */
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}
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static int rt2860_suspend(struct pci_dev *pci_dev, pm_message_t state)
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@@ -146,33 +146,33 @@ static int rt2860_suspend(struct pci_dev *pci_dev, pm_message_t state)
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/* and 1 suspend/resume function for 1 module, not for each interface */
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/* so Linux will call suspend/resume function once */
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if (VIRTUAL_IF_NUM(pAd) > 0) {
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- // avoid users do suspend after interface is down
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+ /* avoid users do suspend after interface is down */
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- // stop interface
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+ /* stop interface */
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netif_carrier_off(net_dev);
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netif_stop_queue(net_dev);
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- // mark device as removed from system and therefore no longer available
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+ /* mark device as removed from system and therefore no longer available */
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netif_device_detach(net_dev);
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- // mark halt flag
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+ /* mark halt flag */
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RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_HALT_IN_PROGRESS);
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RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_RADIO_OFF);
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- // take down the device
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+ /* take down the device */
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rt28xx_close((PNET_DEV) net_dev);
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RT_MOD_DEC_USE_COUNT();
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}
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}
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- // reference to http://vovo2000.com/type-lab/linux/kernel-api/linux-kernel-api.html
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- // enable device to generate PME# when suspended
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- // pci_choose_state(): Choose the power state of a PCI device to be suspended
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+ /* reference to http://vovo2000.com/type-lab/linux/kernel-api/linux-kernel-api.html */
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+ /* enable device to generate PME# when suspended */
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+ /* pci_choose_state(): Choose the power state of a PCI device to be suspended */
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retval = pci_enable_wake(pci_dev, pci_choose_state(pci_dev, state), 1);
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- // save the PCI configuration space of a device before suspending
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+ /* save the PCI configuration space of a device before suspending */
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pci_save_state(pci_dev);
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- // disable PCI device after use
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+ /* disable PCI device after use */
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pci_disable_device(pci_dev);
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retval = pci_set_power_state(pci_dev, pci_choose_state(pci_dev, state));
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@@ -187,22 +187,22 @@ static int rt2860_resume(struct pci_dev *pci_dev)
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PRTMP_ADAPTER pAd = (PRTMP_ADAPTER) NULL;
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INT32 retval;
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- // set the power state of a PCI device
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- // PCI has 4 power states, DO (normal) ~ D3(less power)
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- // in include/linux/pci.h, you can find that
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- // #define PCI_D0 ((pci_power_t __force) 0)
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- // #define PCI_D1 ((pci_power_t __force) 1)
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- // #define PCI_D2 ((pci_power_t __force) 2)
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- // #define PCI_D3hot ((pci_power_t __force) 3)
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- // #define PCI_D3cold ((pci_power_t __force) 4)
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- // #define PCI_UNKNOWN ((pci_power_t __force) 5)
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- // #define PCI_POWER_ERROR ((pci_power_t __force) -1)
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+ /* set the power state of a PCI device */
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+ /* PCI has 4 power states, DO (normal) ~ D3(less power) */
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+ /* in include/linux/pci.h, you can find that */
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+ /* #define PCI_D0 ((pci_power_t __force) 0) */
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+ /* #define PCI_D1 ((pci_power_t __force) 1) */
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+ /* #define PCI_D2 ((pci_power_t __force) 2) */
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+ /* #define PCI_D3hot ((pci_power_t __force) 3) */
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+ /* #define PCI_D3cold ((pci_power_t __force) 4) */
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+ /* #define PCI_UNKNOWN ((pci_power_t __force) 5) */
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+ /* #define PCI_POWER_ERROR ((pci_power_t __force) -1) */
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retval = pci_set_power_state(pci_dev, PCI_D0);
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- // restore the saved state of a PCI device
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+ /* restore the saved state of a PCI device */
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pci_restore_state(pci_dev);
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- // initialize device before it's used by a driver
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+ /* initialize device before it's used by a driver */
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if (pci_enable_device(pci_dev)) {
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printk("pci enable fail!\n");
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return 0;
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@@ -220,16 +220,16 @@ static int rt2860_resume(struct pci_dev *pci_dev)
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/* and 1 suspend/resume function for 1 module, not for each interface */
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/* so Linux will call suspend/resume function once */
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if (VIRTUAL_IF_NUM(pAd) > 0) {
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- // mark device as attached from system and restart if needed
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+ /* mark device as attached from system and restart if needed */
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netif_device_attach(net_dev);
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if (rt28xx_open((PNET_DEV) net_dev) != 0) {
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- // open fail
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+ /* open fail */
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DBGPRINT(RT_DEBUG_TRACE,
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("<=== rt2860_resume()\n"));
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return 0;
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}
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- // increase MODULE use count
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+ /* increase MODULE use count */
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RT_MOD_INC_USE_COUNT();
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RTMP_CLEAR_FLAG(pAd, fRTMP_ADAPTER_HALT_IN_PROGRESS);
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@@ -244,16 +244,16 @@ static int rt2860_resume(struct pci_dev *pci_dev)
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DBGPRINT(RT_DEBUG_TRACE, ("<=== rt2860_resume()\n"));
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return 0;
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}
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-#endif // CONFIG_PM //
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+#endif /* CONFIG_PM // */
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static INT __init rt2860_init_module(VOID)
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{
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return pci_register_driver(&rt2860_driver);
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}
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-//
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-// Driver module unload function
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-//
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+/* */
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+/* Driver module unload function */
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+/* */
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static VOID __exit rt2860_cleanup_module(VOID)
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{
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pci_unregister_driver(&rt2860_driver);
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@@ -262,9 +262,9 @@ static VOID __exit rt2860_cleanup_module(VOID)
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module_init(rt2860_init_module);
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module_exit(rt2860_cleanup_module);
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-//
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-// PCI device probe & initialization function
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-//
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+/* */
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+/* PCI device probe & initialization function */
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+/* */
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static INT __devinit rt2860_probe(IN struct pci_dev *pci_dev,
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IN const struct pci_device_id *pci_id)
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{
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@@ -278,8 +278,8 @@ static INT __devinit rt2860_probe(IN struct pci_dev *pci_dev,
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DBGPRINT(RT_DEBUG_TRACE, ("===> rt2860_probe\n"));
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-//PCIDevInit==============================================
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- // wake up and enable device
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+/*PCIDevInit============================================== */
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+ /* wake up and enable device */
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if ((rv = pci_enable_device(pci_dev)) != 0) {
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DBGPRINT(RT_DEBUG_ERROR,
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("Enable PCI device failed, errno=%d!\n", rv));
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@@ -293,7 +293,7 @@ static INT __devinit rt2860_probe(IN struct pci_dev *pci_dev,
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("Request PCI resource failed, errno=%d!\n", rv));
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goto err_out;
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}
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- // map physical address to virtual address for accessing register
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+ /* map physical address to virtual address for accessing register */
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csr_addr =
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(unsigned long)ioremap(pci_resource_start(pci_dev, 0),
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pci_resource_len(pci_dev, 0));
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@@ -310,11 +310,11 @@ static INT __devinit rt2860_probe(IN struct pci_dev *pci_dev,
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(ULONG) csr_addr, pci_dev->irq));
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}
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- // Set DMA master
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+ /* Set DMA master */
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pci_set_master(pci_dev);
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-//RtmpDevInit==============================================
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- // Allocate RTMP_ADAPTER adapter structure
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+/*RtmpDevInit============================================== */
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+ /* Allocate RTMP_ADAPTER adapter structure */
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handle = kmalloc(sizeof(struct os_cookie), GFP_KERNEL);
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if (handle == NULL) {
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DBGPRINT(RT_DEBUG_ERROR,
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@@ -325,25 +325,25 @@ static INT __devinit rt2860_probe(IN struct pci_dev *pci_dev,
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((POS_COOKIE) handle)->pci_dev = pci_dev;
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- rv = RTMPAllocAdapterBlock(handle, &pAd); //shiang: we may need the pci_dev for allocate structure of "RTMP_ADAPTER"
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+ rv = RTMPAllocAdapterBlock(handle, &pAd); /*shiang: we may need the pci_dev for allocate structure of "RTMP_ADAPTER" */
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if (rv != NDIS_STATUS_SUCCESS)
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goto err_out_iounmap;
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- // Here are the RTMP_ADAPTER structure with pci-bus specific parameters.
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+ /* Here are the RTMP_ADAPTER structure with pci-bus specific parameters. */
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pAd->CSRBaseAddress = (PUCHAR) csr_addr;
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DBGPRINT(RT_DEBUG_ERROR,
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("pAd->CSRBaseAddress =0x%lx, csr_addr=0x%lx!\n",
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(ULONG) pAd->CSRBaseAddress, csr_addr));
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RtmpRaDevCtrlInit(pAd, RTMP_DEV_INF_PCI);
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-//NetDevInit==============================================
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+/*NetDevInit============================================== */
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net_dev = RtmpPhyNetDevInit(pAd, &netDevHook);
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if (net_dev == NULL)
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goto err_out_free_radev;
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- // Here are the net_device structure with pci-bus specific parameters.
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- net_dev->irq = pci_dev->irq; // Interrupt IRQ number
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- net_dev->base_addr = csr_addr; // Save CSR virtual address and irq to device structure
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- pci_set_drvdata(pci_dev, net_dev); // Set driver data
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+ /* Here are the net_device structure with pci-bus specific parameters. */
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+ net_dev->irq = pci_dev->irq; /* Interrupt IRQ number */
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+ net_dev->base_addr = csr_addr; /* Save CSR virtual address and irq to device structure */
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+ pci_set_drvdata(pci_dev, net_dev); /* Set driver data */
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/* for supporting Network Manager */
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/* Set the sysfs physical device reference for the network logical device
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@@ -351,8 +351,8 @@ static INT __devinit rt2860_probe(IN struct pci_dev *pci_dev,
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*/
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SET_NETDEV_DEV(net_dev, &(pci_dev->dev));
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-//All done, it's time to register the net device to linux kernel.
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- // Register this device
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+/*All done, it's time to register the net device to linux kernel. */
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+ /* Register this device */
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rv = RtmpOSNetDevAttach(net_dev, &netDevHook);
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if (rv)
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goto err_out_free_netdev;
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@@ -362,7 +362,7 @@ static INT __devinit rt2860_probe(IN struct pci_dev *pci_dev,
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DBGPRINT(RT_DEBUG_TRACE, ("<=== rt2860_probe\n"));
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- return 0; // probe ok
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+ return 0; /* probe ok */
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/* --------------------------- ERROR HANDLE --------------------------- */
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err_out_free_netdev:
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@@ -393,39 +393,39 @@ static VOID __devexit rt2860_remove_one(IN struct pci_dev *pci_dev)
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{
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PNET_DEV net_dev = pci_get_drvdata(pci_dev);
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RTMP_ADAPTER *pAd = NULL;
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- ULONG csr_addr = net_dev->base_addr; // pAd->CSRBaseAddress;
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+ ULONG csr_addr = net_dev->base_addr; /* pAd->CSRBaseAddress; */
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GET_PAD_FROM_NET_DEV(pAd, net_dev);
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DBGPRINT(RT_DEBUG_TRACE, ("===> rt2860_remove_one\n"));
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if (pAd != NULL) {
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- // Unregister/Free all allocated net_device.
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+ /* Unregister/Free all allocated net_device. */
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RtmpPhyNetDevExit(pAd, net_dev);
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- // Unmap CSR base address
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+ /* Unmap CSR base address */
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iounmap((char *)(csr_addr));
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- // release memory region
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+ /* release memory region */
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release_mem_region(pci_resource_start(pci_dev, 0),
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pci_resource_len(pci_dev, 0));
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- // Free RTMP_ADAPTER related structures.
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+ /* Free RTMP_ADAPTER related structures. */
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RtmpRaDevCtrlExit(pAd);
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} else {
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- // Unregister network device
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+ /* Unregister network device */
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RtmpOSNetDevDetach(net_dev);
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- // Unmap CSR base address
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+ /* Unmap CSR base address */
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iounmap((char *)(net_dev->base_addr));
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- // release memory region
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+ /* release memory region */
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release_mem_region(pci_resource_start(pci_dev, 0),
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pci_resource_len(pci_dev, 0));
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}
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- // Free the root net_device
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+ /* Free the root net_device */
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RtmpOSNetDevFree(net_dev);
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}
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@@ -475,7 +475,7 @@ static VOID RTMPInitPCIeDevice(IN struct pci_dev *pci_dev, IN PRTMP_ADAPTER pAd)
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(device_id == NIC3090_PCIe_DEVICE_ID) ||
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(device_id == NIC3091_PCIe_DEVICE_ID) ||
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(device_id == NIC3092_PCIe_DEVICE_ID) ||
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-#endif // RT3090 //
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+#endif /* RT3090 // */
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0) {
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UINT32 MacCsr0 = 0, Index = 0;
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do {
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@@ -487,8 +487,8 @@ static VOID RTMPInitPCIeDevice(IN struct pci_dev *pci_dev, IN PRTMP_ADAPTER pAd)
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RTMPusecDelay(10);
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|
} while (Index++ < 100);
|
|
|
|
|
|
- // Support advanced power save after 2892/2790.
|
|
|
- // MAC version at offset 0x1000 is 0x2872XXXX/0x2870XXXX(PCIe, USB, SDIO).
|
|
|
+ /* Support advanced power save after 2892/2790. */
|
|
|
+ /* MAC version at offset 0x1000 is 0x2872XXXX/0x2870XXXX(PCIe, USB, SDIO). */
|
|
|
if ((MacCsr0 & 0xffff0000) != 0x28600000) {
|
|
|
OPSTATUS_SET_FLAG(pAd, fOP_STATUS_PCIE_DEVICE);
|
|
|
}
|
|
@@ -509,7 +509,7 @@ VOID RTMPInitPCIeLinkCtrlValue(IN PRTMP_ADAPTER pAd)
|
|
|
return;
|
|
|
|
|
|
DBGPRINT(RT_DEBUG_TRACE, ("%s.===>\n", __func__));
|
|
|
- // Init EEPROM, and save settings
|
|
|
+ /* Init EEPROM, and save settings */
|
|
|
if (!(IS_RT3090(pAd) || IS_RT3572(pAd) || IS_RT3390(pAd))) {
|
|
|
RT28xx_EEPROM_READ16(pAd, 0x22, PCIePowerSaveLevel);
|
|
|
pAd->PCIePowerSaveLevel = PCIePowerSaveLevel & 0xff;
|
|
@@ -541,16 +541,16 @@ VOID RTMPInitPCIeLinkCtrlValue(IN PRTMP_ADAPTER pAd)
|
|
|
PCIePowerSaveLevel &= 0xff;
|
|
|
PCIePowerSaveLevel = PCIePowerSaveLevel >> 6;
|
|
|
switch (PCIePowerSaveLevel) {
|
|
|
- case 0: // Only support L0
|
|
|
+ case 0: /* Only support L0 */
|
|
|
pAd->LnkCtrlBitMask = 0;
|
|
|
break;
|
|
|
- case 1: // Only enable L0s
|
|
|
+ case 1: /* Only enable L0s */
|
|
|
pAd->LnkCtrlBitMask = 1;
|
|
|
break;
|
|
|
- case 2: // enable L1, L0s
|
|
|
+ case 2: /* enable L1, L0s */
|
|
|
pAd->LnkCtrlBitMask = 3;
|
|
|
break;
|
|
|
- case 3: // sync with host clk and enable L1, L0s
|
|
|
+ case 3: /* sync with host clk and enable L1, L0s */
|
|
|
pAd->LnkCtrlBitMask = 0x103;
|
|
|
break;
|
|
|
}
|
|
@@ -580,7 +580,7 @@ VOID RTMPInitPCIeLinkCtrlValue(IN PRTMP_ADAPTER pAd)
|
|
|
} else if (IS_RT3090(pAd) || IS_RT3572(pAd) || IS_RT3390(pAd)) {
|
|
|
UCHAR LinkCtrlSetting = 0;
|
|
|
|
|
|
- // Check 3090E special setting chip.
|
|
|
+ /* Check 3090E special setting chip. */
|
|
|
RT28xx_EEPROM_READ16(pAd, 0x24, data2);
|
|
|
if ((data2 == 0x9280) && ((pAd->MACVersion & 0xffff) == 0x0211)) {
|
|
|
pAd->b3090ESpecialChip = TRUE;
|
|
@@ -588,37 +588,37 @@ VOID RTMPInitPCIeLinkCtrlValue(IN PRTMP_ADAPTER pAd)
|
|
|
}
|
|
|
|
|
|
RTMP_IO_READ32(pAd, AUX_CTRL, &MacValue);
|
|
|
- //enable WAKE_PCIE function, which forces to enable PCIE clock when mpu interrupt asserting.
|
|
|
- //Force PCIE 125MHz CLK to toggle
|
|
|
+ /*enable WAKE_PCIE function, which forces to enable PCIE clock when mpu interrupt asserting. */
|
|
|
+ /*Force PCIE 125MHz CLK to toggle */
|
|
|
MacValue |= 0x402;
|
|
|
RTMP_IO_WRITE32(pAd, AUX_CTRL, MacValue);
|
|
|
DBGPRINT_RAW(RT_DEBUG_ERROR,
|
|
|
(" AUX_CTRL = 0x%32x\n", MacValue));
|
|
|
|
|
|
- // for RT30xx F and after, PCIe infterface, and for power solution 3
|
|
|
+ /* for RT30xx F and after, PCIe infterface, and for power solution 3 */
|
|
|
if ((IS_VERSION_AFTER_F(pAd))
|
|
|
&& (pAd->StaCfg.PSControl.field.rt30xxPowerMode >= 2)
|
|
|
&& (pAd->StaCfg.PSControl.field.rt30xxPowerMode <= 3)) {
|
|
|
RTMP_IO_READ32(pAd, AUX_CTRL, &MacValue);
|
|
|
DBGPRINT_RAW(RT_DEBUG_ERROR,
|
|
|
(" Read AUX_CTRL = 0x%x\n", MacValue));
|
|
|
- // turn on bit 12.
|
|
|
- //enable 32KHz clock mode for power saving
|
|
|
+ /* turn on bit 12. */
|
|
|
+ /*enable 32KHz clock mode for power saving */
|
|
|
MacValue |= 0x1000;
|
|
|
if (MacValue != 0xffffffff) {
|
|
|
RTMP_IO_WRITE32(pAd, AUX_CTRL, MacValue);
|
|
|
DBGPRINT_RAW(RT_DEBUG_ERROR,
|
|
|
(" Write AUX_CTRL = 0x%x\n",
|
|
|
MacValue));
|
|
|
- // 1. if use PCIePowerSetting is 2 or 3, need to program OSC_CTRL to 0x3ff11.
|
|
|
+ /* 1. if use PCIePowerSetting is 2 or 3, need to program OSC_CTRL to 0x3ff11. */
|
|
|
MacValue = 0x3ff11;
|
|
|
RTMP_IO_WRITE32(pAd, OSC_CTRL, MacValue);
|
|
|
DBGPRINT_RAW(RT_DEBUG_ERROR,
|
|
|
(" OSC_CTRL = 0x%x\n", MacValue));
|
|
|
- // 2. Write PCI register Clk ref bit
|
|
|
+ /* 2. Write PCI register Clk ref bit */
|
|
|
RTMPrt3xSetPCIePowerLinkCtrl(pAd);
|
|
|
} else {
|
|
|
- // Error read Aux_Ctrl value. Force to use solution 1
|
|
|
+ /* Error read Aux_Ctrl value. Force to use solution 1 */
|
|
|
DBGPRINT(RT_DEBUG_ERROR,
|
|
|
(" Error Value in AUX_CTRL = 0x%x\n",
|
|
|
MacValue));
|
|
@@ -627,20 +627,20 @@ VOID RTMPInitPCIeLinkCtrlValue(IN PRTMP_ADAPTER pAd)
|
|
|
(" Force to use power solution1 \n"));
|
|
|
}
|
|
|
}
|
|
|
- // 1. read setting from inf file.
|
|
|
+ /* 1. read setting from inf file. */
|
|
|
|
|
|
PCIePowerSaveLevel =
|
|
|
(USHORT) pAd->StaCfg.PSControl.field.rt30xxPowerMode;
|
|
|
DBGPRINT(RT_DEBUG_ERROR,
|
|
|
("====> rt30xx Read PowerLevelMode = 0x%x.\n",
|
|
|
PCIePowerSaveLevel));
|
|
|
- // 2. Check EnableNewPS.
|
|
|
+ /* 2. Check EnableNewPS. */
|
|
|
if (pAd->StaCfg.PSControl.field.EnableNewPS == FALSE)
|
|
|
PCIePowerSaveLevel = 1;
|
|
|
|
|
|
if (IS_VERSION_BEFORE_F(pAd)
|
|
|
&& (pAd->b3090ESpecialChip == FALSE)) {
|
|
|
- // Chip Version E only allow 1, So force set 1.
|
|
|
+ /* Chip Version E only allow 1, So force set 1. */
|
|
|
PCIePowerSaveLevel &= 0x1;
|
|
|
pAd->PCIePowerSaveLevel = (USHORT) PCIePowerSaveLevel;
|
|
|
DBGPRINT(RT_DEBUG_TRACE,
|
|
@@ -650,7 +650,7 @@ VOID RTMPInitPCIeLinkCtrlValue(IN PRTMP_ADAPTER pAd)
|
|
|
AsicSendCommandToMcu(pAd, 0x83, 0xff,
|
|
|
(UCHAR) PCIePowerSaveLevel, 0x00);
|
|
|
} else {
|
|
|
- // Chip Version F and after only allow 1 or 2 or 3. This might be modified after new chip version come out.
|
|
|
+ /* Chip Version F and after only allow 1 or 2 or 3. This might be modified after new chip version come out. */
|
|
|
if (!
|
|
|
((PCIePowerSaveLevel == 1)
|
|
|
|| (PCIePowerSaveLevel == 3)))
|
|
@@ -659,8 +659,8 @@ VOID RTMPInitPCIeLinkCtrlValue(IN PRTMP_ADAPTER pAd)
|
|
|
("====> rt30xx F Write 0x83 Command = 0x%x.\n",
|
|
|
PCIePowerSaveLevel));
|
|
|
pAd->PCIePowerSaveLevel = (USHORT) PCIePowerSaveLevel;
|
|
|
- // for 3090F , we need to add high-byte arg for 0x83 command to indicate the link control setting in
|
|
|
- // PCI Configuration Space. Because firmware can't read PCI Configuration Space
|
|
|
+ /* for 3090F , we need to add high-byte arg for 0x83 command to indicate the link control setting in */
|
|
|
+ /* PCI Configuration Space. Because firmware can't read PCI Configuration Space */
|
|
|
if ((pAd->Rt3xxRalinkLinkCtrl & 0x2)
|
|
|
&& (pAd->Rt3xxHostLinkCtrl & 0x2)) {
|
|
|
LinkCtrlSetting = 1;
|
|
@@ -673,11 +673,11 @@ VOID RTMPInitPCIeLinkCtrlValue(IN PRTMP_ADAPTER pAd)
|
|
|
LinkCtrlSetting);
|
|
|
}
|
|
|
}
|
|
|
- // Find Ralink PCIe Device's Express Capability Offset
|
|
|
+ /* Find Ralink PCIe Device's Express Capability Offset */
|
|
|
pos = pci_find_capability(pObj->pci_dev, PCI_CAP_ID_EXP);
|
|
|
|
|
|
if (pos != 0) {
|
|
|
- // Ralink PCIe Device's Link Control Register Offset
|
|
|
+ /* Ralink PCIe Device's Link Control Register Offset */
|
|
|
pAd->RLnkCtrlOffset = pos + PCI_EXP_LNKCTL;
|
|
|
pci_read_config_word(pObj->pci_dev, pAd->RLnkCtrlOffset,
|
|
|
®16);
|
|
@@ -698,7 +698,7 @@ VOID RTMPInitPCIeLinkCtrlValue(IN PRTMP_ADAPTER pAd)
|
|
|
("Write (Ralink PCIe Link Control Register) offset 0x%x = 0x%x\n",
|
|
|
pos + PCI_EXP_LNKCTL, Configuration));
|
|
|
}
|
|
|
-#endif // RT2860 //
|
|
|
+#endif /* RT2860 // */
|
|
|
|
|
|
RTMPFindHostPCIDev(pAd);
|
|
|
if (pObj->parent_pci_dev) {
|
|
@@ -711,14 +711,14 @@ VOID RTMPInitPCIeLinkCtrlValue(IN PRTMP_ADAPTER pAd)
|
|
|
bFindIntel = TRUE;
|
|
|
RTMP_SET_PSFLAG(pAd, fRTMP_PS_TOGGLE_L1);
|
|
|
}
|
|
|
- // Find PCI-to-PCI Bridge Express Capability Offset
|
|
|
+ /* Find PCI-to-PCI Bridge Express Capability Offset */
|
|
|
pos =
|
|
|
pci_find_capability(pObj->parent_pci_dev,
|
|
|
PCI_CAP_ID_EXP);
|
|
|
|
|
|
if (pos != 0) {
|
|
|
BOOLEAN bChange = FALSE;
|
|
|
- // PCI-to-PCI Bridge Link Control Register Offset
|
|
|
+ /* PCI-to-PCI Bridge Link Control Register Offset */
|
|
|
pAd->HostLnkCtrlOffset = pos + PCI_EXP_LNKCTL;
|
|
|
pci_read_config_word(pObj->parent_pci_dev,
|
|
|
pAd->HostLnkCtrlOffset,
|
|
@@ -739,7 +739,7 @@ VOID RTMPInitPCIeLinkCtrlValue(IN PRTMP_ADAPTER pAd)
|
|
|
case NIC2790_PCIe_DEVICE_ID:
|
|
|
bChange = TRUE;
|
|
|
break;
|
|
|
-#endif // RT2860 //
|
|
|
+#endif /* RT2860 // */
|
|
|
#ifdef RT3090
|
|
|
case NIC3090_PCIe_DEVICE_ID:
|
|
|
case NIC3091_PCIe_DEVICE_ID:
|
|
@@ -747,7 +747,7 @@ VOID RTMPInitPCIeLinkCtrlValue(IN PRTMP_ADAPTER pAd)
|
|
|
if (bFindIntel == FALSE)
|
|
|
bChange = TRUE;
|
|
|
break;
|
|
|
-#endif // RT3090 //
|
|
|
+#endif /* RT3090 // */
|
|
|
default:
|
|
|
break;
|
|
|
}
|
|
@@ -782,14 +782,14 @@ VOID RTMPInitPCIeLinkCtrlValue(IN PRTMP_ADAPTER pAd)
|
|
|
if (bFindIntel == FALSE) {
|
|
|
DBGPRINT(RT_DEBUG_TRACE,
|
|
|
("Doesn't find Intel PCI host controller. \n"));
|
|
|
- // Doesn't switch L0, L1, So set PCIePowerSaveLevel to 0xff
|
|
|
+ /* Doesn't switch L0, L1, So set PCIePowerSaveLevel to 0xff */
|
|
|
pAd->PCIePowerSaveLevel = 0xff;
|
|
|
if ((pAd->RLnkCtrlOffset != 0)
|
|
|
#ifdef RT3090
|
|
|
&& ((pObj->DeviceID == NIC3090_PCIe_DEVICE_ID)
|
|
|
|| (pObj->DeviceID == NIC3091_PCIe_DEVICE_ID)
|
|
|
|| (pObj->DeviceID == NIC3092_PCIe_DEVICE_ID))
|
|
|
-#endif // RT3090 //
|
|
|
+#endif /* RT3090 // */
|
|
|
) {
|
|
|
pci_read_config_word(pObj->pci_dev, pAd->RLnkCtrlOffset,
|
|
|
®16);
|
|
@@ -871,20 +871,20 @@ VOID RTMPPCIeLinkCtrlValueRestore(IN PRTMP_ADAPTER pAd, IN UCHAR Level)
|
|
|
if (!((pObj->DeviceID == NIC2860_PCIe_DEVICE_ID)
|
|
|
|| (pObj->DeviceID == NIC2790_PCIe_DEVICE_ID)))
|
|
|
return;
|
|
|
-#endif // RT2860 //
|
|
|
- // Check PSControl Configuration
|
|
|
+#endif /* RT2860 // */
|
|
|
+ /* Check PSControl Configuration */
|
|
|
if (pAd->StaCfg.PSControl.field.EnableNewPS == FALSE)
|
|
|
return;
|
|
|
|
|
|
- //3090 will not execute the following codes.
|
|
|
- // Check interface : If not PCIe interface, return.
|
|
|
+ /*3090 will not execute the following codes. */
|
|
|
+ /* Check interface : If not PCIe interface, return. */
|
|
|
|
|
|
#ifdef RT3090
|
|
|
if ((pObj->DeviceID == NIC3090_PCIe_DEVICE_ID)
|
|
|
|| (pObj->DeviceID == NIC3091_PCIe_DEVICE_ID)
|
|
|
|| (pObj->DeviceID == NIC3092_PCIe_DEVICE_ID))
|
|
|
return;
|
|
|
-#endif // RT3090 //
|
|
|
+#endif /* RT3090 // */
|
|
|
|
|
|
DBGPRINT(RT_DEBUG_TRACE, ("%s.===>\n", __func__));
|
|
|
PCIePowerSaveLevel = pAd->PCIePowerSaveLevel;
|
|
@@ -898,7 +898,7 @@ VOID RTMPPCIeLinkCtrlValueRestore(IN PRTMP_ADAPTER pAd, IN UCHAR Level)
|
|
|
Configuration);
|
|
|
if ((Configuration != 0) && (Configuration != 0xFFFF)) {
|
|
|
Configuration &= 0xfefc;
|
|
|
- // If call from interface down, restore to orginial setting.
|
|
|
+ /* If call from interface down, restore to orginial setting. */
|
|
|
if (Level == RESTORE_CLOSE) {
|
|
|
Configuration |= pAd->HostLnkCtrlConfiguration;
|
|
|
} else
|
|
@@ -920,7 +920,7 @@ VOID RTMPPCIeLinkCtrlValueRestore(IN PRTMP_ADAPTER pAd, IN UCHAR Level)
|
|
|
Configuration);
|
|
|
if ((Configuration != 0) && (Configuration != 0xFFFF)) {
|
|
|
Configuration &= 0xfefc;
|
|
|
- // If call from interface down, restore to orginial setting.
|
|
|
+ /* If call from interface down, restore to orginial setting. */
|
|
|
if (Level == RESTORE_CLOSE)
|
|
|
Configuration |= pAd->RLnkCtrlConfiguration;
|
|
|
else
|
|
@@ -965,20 +965,20 @@ VOID RTMPPCIeLinkCtrlSetting(IN PRTMP_ADAPTER pAd, IN USHORT Max)
|
|
|
if (!((pObj->DeviceID == NIC2860_PCIe_DEVICE_ID)
|
|
|
|| (pObj->DeviceID == NIC2790_PCIe_DEVICE_ID)))
|
|
|
return;
|
|
|
-#endif // RT2860 //
|
|
|
- // Check PSControl Configuration
|
|
|
+#endif /* RT2860 // */
|
|
|
+ /* Check PSControl Configuration */
|
|
|
if (pAd->StaCfg.PSControl.field.EnableNewPS == FALSE)
|
|
|
return;
|
|
|
|
|
|
- // Check interface : If not PCIe interface, return.
|
|
|
- //Block 3090 to enter the following function
|
|
|
+ /* Check interface : If not PCIe interface, return. */
|
|
|
+ /*Block 3090 to enter the following function */
|
|
|
|
|
|
#ifdef RT3090
|
|
|
if ((pObj->DeviceID == NIC3090_PCIe_DEVICE_ID)
|
|
|
|| (pObj->DeviceID == NIC3091_PCIe_DEVICE_ID)
|
|
|
|| (pObj->DeviceID == NIC3092_PCIe_DEVICE_ID))
|
|
|
return;
|
|
|
-#endif // RT3090 //
|
|
|
+#endif /* RT3090 // */
|
|
|
if (!RTMP_TEST_PSFLAG(pAd, fRTMP_PS_CAN_GO_SLEEP)) {
|
|
|
DBGPRINT(RT_DEBUG_INFO,
|
|
|
("RTMPPCIePowerLinkCtrl return on fRTMP_PS_CAN_GO_SLEEP flag\n"));
|
|
@@ -993,27 +993,27 @@ VOID RTMPPCIeLinkCtrlSetting(IN PRTMP_ADAPTER pAd, IN USHORT Max)
|
|
|
}
|
|
|
PCIePowerSaveLevel = PCIePowerSaveLevel >> 6;
|
|
|
|
|
|
- // Skip non-exist deice right away
|
|
|
+ /* Skip non-exist deice right away */
|
|
|
if (pObj->parent_pci_dev && (pAd->HostLnkCtrlOffset != 0)) {
|
|
|
PCI_REG_READ_WORD(pObj->parent_pci_dev, pAd->HostLnkCtrlOffset,
|
|
|
Configuration);
|
|
|
switch (PCIePowerSaveLevel) {
|
|
|
case 0:
|
|
|
- // Set b0 and b1 of LinkControl (both 2892 and PCIe bridge) to 00
|
|
|
+ /* Set b0 and b1 of LinkControl (both 2892 and PCIe bridge) to 00 */
|
|
|
Configuration &= 0xfefc;
|
|
|
break;
|
|
|
case 1:
|
|
|
- // Set b0 and b1 of LinkControl (both 2892 and PCIe bridge) to 01
|
|
|
+ /* Set b0 and b1 of LinkControl (both 2892 and PCIe bridge) to 01 */
|
|
|
Configuration &= 0xfefc;
|
|
|
Configuration |= 0x1;
|
|
|
break;
|
|
|
case 2:
|
|
|
- // Set b0 and b1 of LinkControl (both 2892 and PCIe bridge) to 11
|
|
|
+ /* Set b0 and b1 of LinkControl (both 2892 and PCIe bridge) to 11 */
|
|
|
Configuration &= 0xfefc;
|
|
|
Configuration |= 0x3;
|
|
|
break;
|
|
|
case 3:
|
|
|
- // Set b0 and b1 of LinkControl (both 2892 and PCIe bridge) to 11 and bit 8 of LinkControl of 2892 to 1
|
|
|
+ /* Set b0 and b1 of LinkControl (both 2892 and PCIe bridge) to 11 and bit 8 of LinkControl of 2892 to 1 */
|
|
|
Configuration &= 0xfefc;
|
|
|
Configuration |= 0x103;
|
|
|
break;
|
|
@@ -1026,7 +1026,7 @@ VOID RTMPPCIeLinkCtrlSetting(IN PRTMP_ADAPTER pAd, IN USHORT Max)
|
|
|
}
|
|
|
|
|
|
if (pObj->pci_dev && (pAd->RLnkCtrlOffset != 0)) {
|
|
|
- // first 2892 chip not allow to frequently set mode 3. will cause hang problem.
|
|
|
+ /* first 2892 chip not allow to frequently set mode 3. will cause hang problem. */
|
|
|
if (PCIePowerSaveLevel > Max)
|
|
|
PCIePowerSaveLevel = Max;
|
|
|
|
|
@@ -1034,25 +1034,25 @@ VOID RTMPPCIeLinkCtrlSetting(IN PRTMP_ADAPTER pAd, IN USHORT Max)
|
|
|
Configuration);
|
|
|
switch (PCIePowerSaveLevel) {
|
|
|
case 0:
|
|
|
- // No PCI power safe
|
|
|
- // Set b0 and b1 of LinkControl (both 2892 and PCIe bridge) to 00 .
|
|
|
+ /* No PCI power safe */
|
|
|
+ /* Set b0 and b1 of LinkControl (both 2892 and PCIe bridge) to 00 . */
|
|
|
Configuration &= 0xfefc;
|
|
|
break;
|
|
|
case 1:
|
|
|
- // L0
|
|
|
- // Set b0 and b1 of LinkControl (both 2892 and PCIe bridge) to 01 .
|
|
|
+ /* L0 */
|
|
|
+ /* Set b0 and b1 of LinkControl (both 2892 and PCIe bridge) to 01 . */
|
|
|
Configuration &= 0xfefc;
|
|
|
Configuration |= 0x1;
|
|
|
break;
|
|
|
case 2:
|
|
|
- // L0 and L1
|
|
|
- // Set b0 and b1 of LinkControl (both 2892 and PCIe bridge) to 11
|
|
|
+ /* L0 and L1 */
|
|
|
+ /* Set b0 and b1 of LinkControl (both 2892 and PCIe bridge) to 11 */
|
|
|
Configuration &= 0xfefc;
|
|
|
Configuration |= 0x3;
|
|
|
break;
|
|
|
case 3:
|
|
|
- // L0 , L1 and clock management.
|
|
|
- // Set b0 and b1 of LinkControl (both 2892 and PCIe bridge) to 11 and bit 8 of LinkControl of 2892 to 1
|
|
|
+ /* L0 , L1 and clock management. */
|
|
|
+ /* Set b0 and b1 of LinkControl (both 2892 and PCIe bridge) to 11 and bit 8 of LinkControl of 2892 to 1 */
|
|
|
Configuration &= 0xfefc;
|
|
|
Configuration |= 0x103;
|
|
|
pAd->bPCIclkOff = TRUE;
|
|
@@ -1091,35 +1091,35 @@ VOID RTMPrt3xSetPCIePowerLinkCtrl(IN PRTMP_ADAPTER pAd)
|
|
|
("RTMPrt3xSetPCIePowerLinkCtrl.===> %lx\n",
|
|
|
pAd->StaCfg.PSControl.word));
|
|
|
|
|
|
- // Check PSControl Configuration
|
|
|
+ /* Check PSControl Configuration */
|
|
|
if (pAd->StaCfg.PSControl.field.EnableNewPS == FALSE)
|
|
|
return;
|
|
|
RTMPFindHostPCIDev(pAd);
|
|
|
if (pObj->parent_pci_dev) {
|
|
|
- // Find PCI-to-PCI Bridge Express Capability Offset
|
|
|
+ /* Find PCI-to-PCI Bridge Express Capability Offset */
|
|
|
pos = pci_find_capability(pObj->parent_pci_dev, PCI_CAP_ID_EXP);
|
|
|
|
|
|
if (pos != 0) {
|
|
|
pAd->HostLnkCtrlOffset = pos + PCI_EXP_LNKCTL;
|
|
|
}
|
|
|
- // If configurared to turn on L1.
|
|
|
+ /* If configurared to turn on L1. */
|
|
|
HostConfiguration = 0;
|
|
|
if (pAd->StaCfg.PSControl.field.rt30xxForceASPMTest == 1) {
|
|
|
DBGPRINT(RT_DEBUG_TRACE, ("Enter,PSM : Force ASPM \n"));
|
|
|
|
|
|
- // Skip non-exist deice right away
|
|
|
+ /* Skip non-exist deice right away */
|
|
|
if ((pAd->HostLnkCtrlOffset != 0)) {
|
|
|
PCI_REG_READ_WORD(pObj->parent_pci_dev,
|
|
|
pAd->HostLnkCtrlOffset,
|
|
|
HostConfiguration);
|
|
|
- // Prepare Configuration to write to Host
|
|
|
+ /* Prepare Configuration to write to Host */
|
|
|
HostConfiguration |= 0x3;
|
|
|
PCI_REG_WIRTE_WORD(pObj->parent_pci_dev,
|
|
|
pAd->HostLnkCtrlOffset,
|
|
|
HostConfiguration);
|
|
|
pAd->Rt3xxHostLinkCtrl = HostConfiguration;
|
|
|
- // Because in rt30xxForceASPMTest Mode, Force turn on L0s, L1.
|
|
|
- // Fix HostConfiguration bit0:1 = 0x3 for later use.
|
|
|
+ /* Because in rt30xxForceASPMTest Mode, Force turn on L0s, L1. */
|
|
|
+ /* Fix HostConfiguration bit0:1 = 0x3 for later use. */
|
|
|
HostConfiguration = 0x3;
|
|
|
DBGPRINT(RT_DEBUG_TRACE,
|
|
|
("PSM : Force ASPM : "
|
|
@@ -1129,7 +1129,7 @@ VOID RTMPrt3xSetPCIePowerLinkCtrl(IN PRTMP_ADAPTER pAd)
|
|
|
} else if (pAd->StaCfg.PSControl.field.rt30xxFollowHostASPM ==
|
|
|
1) {
|
|
|
|
|
|
- // Skip non-exist deice right away
|
|
|
+ /* Skip non-exist deice right away */
|
|
|
if ((pAd->HostLnkCtrlOffset != 0)) {
|
|
|
PCI_REG_READ_WORD(pObj->parent_pci_dev,
|
|
|
pAd->HostLnkCtrlOffset,
|
|
@@ -1143,12 +1143,12 @@ VOID RTMPrt3xSetPCIePowerLinkCtrl(IN PRTMP_ADAPTER pAd)
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
- // Prepare to write Ralink setting.
|
|
|
- // Find Ralink PCIe Device's Express Capability Offset
|
|
|
+ /* Prepare to write Ralink setting. */
|
|
|
+ /* Find Ralink PCIe Device's Express Capability Offset */
|
|
|
pos = pci_find_capability(pObj->pci_dev, PCI_CAP_ID_EXP);
|
|
|
|
|
|
if (pos != 0) {
|
|
|
- // Ralink PCIe Device's Link Control Register Offset
|
|
|
+ /* Ralink PCIe Device's Link Control Register Offset */
|
|
|
pAd->RLnkCtrlOffset = pos + PCI_EXP_LNKCTL;
|
|
|
pci_read_config_word(pObj->pci_dev, pAd->RLnkCtrlOffset,
|
|
|
®16);
|