|
@@ -38,6 +38,23 @@
|
|
|
pinctrl-single,register-width = <32>;
|
|
|
pinctrl-single,function-mask = <0xffffffff>;
|
|
|
status = "disabled";
|
|
|
+
|
|
|
+ nand_cs3_pins: pinmux_nand_pins {
|
|
|
+ pinctrl-single,bits = <
|
|
|
+ /* EMA_OE, EMA_WE */
|
|
|
+ 0x1c 0x00110000 0x00ff0000
|
|
|
+ /* EMA_CS[4],EMA_CS[3]*/
|
|
|
+ 0x1c 0x00000110 0x00000ff0
|
|
|
+ /*
|
|
|
+ * EMA_D[0], EMA_D[1], EMA_D[2],
|
|
|
+ * EMA_D[3], EMA_D[4], EMA_D[5],
|
|
|
+ * EMA_D[6], EMA_D[7]
|
|
|
+ */
|
|
|
+ 0x24 0x11111111 0xffffffff
|
|
|
+ /* EMA_A[1], EMA_A[2] */
|
|
|
+ 0x30 0x01100000 0x0ff00000
|
|
|
+ >;
|
|
|
+ };
|
|
|
};
|
|
|
serial0: serial@1c42000 {
|
|
|
compatible = "ns16550a";
|
|
@@ -67,4 +84,17 @@
|
|
|
status = "disabled";
|
|
|
};
|
|
|
};
|
|
|
+ nand_cs3@62000000 {
|
|
|
+ compatible = "ti,davinci-nand";
|
|
|
+ reg = <0x62000000 0x807ff
|
|
|
+ 0x68000000 0x8000>;
|
|
|
+ ti,davinci-chipselect = <1>;
|
|
|
+ ti,davinci-mask-ale = <0>;
|
|
|
+ ti,davinci-mask-cle = <0>;
|
|
|
+ ti,davinci-mask-chipsel = <0>;
|
|
|
+ ti,davinci-ecc-mode = "hw";
|
|
|
+ ti,davinci-ecc-bits = <4>;
|
|
|
+ ti,davinci-nand-use-bbt;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
};
|