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@@ -37,6 +37,10 @@ static struct omap_sdrc_params *sdrc_init_params;
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void __iomem *omap2_sdrc_base;
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void __iomem *omap2_sms_base;
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+/* SDRC_POWER register bits */
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+#define SDRC_POWER_EXTCLKDIS_SHIFT 3
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+#define SDRC_POWER_PWDENA_SHIFT 2
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+#define SDRC_POWER_PAGEPOLICY_SHIFT 0
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/**
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* omap2_sdrc_get_params - return SDRC register values for a given clock rate
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@@ -74,7 +78,14 @@ void __init omap2_set_globals_sdrc(struct omap_globals *omap2_globals)
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omap2_sms_base = omap2_globals->sms;
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}
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-/* turn on smart idle modes for SDRAM scheduler and controller */
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+/**
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+ * omap2_sdrc_init - initialize SMS, SDRC devices on boot
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+ * @sp: pointer to a null-terminated list of struct omap_sdrc_params
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+ *
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+ * Turn on smart idle modes for SDRAM scheduler and controller.
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+ * Program a known-good configuration for the SDRC to deal with buggy
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+ * bootloaders.
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+ */
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void __init omap2_sdrc_init(struct omap_sdrc_params *sp)
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{
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u32 l;
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@@ -90,4 +101,10 @@ void __init omap2_sdrc_init(struct omap_sdrc_params *sp)
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sdrc_write_reg(l, SDRC_SYSCONFIG);
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sdrc_init_params = sp;
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+
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+ /* XXX Enable SRFRONIDLEREQ here also? */
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+ l = (1 << SDRC_POWER_EXTCLKDIS_SHIFT) |
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+ (1 << SDRC_POWER_PWDENA_SHIFT) |
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+ (1 << SDRC_POWER_PAGEPOLICY_SHIFT);
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+ sdrc_write_reg(l, SDRC_POWER);
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}
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