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@@ -32,8 +32,35 @@
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#define SLCR_UNLOCK_MAGIC 0xDF0D
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#define SLCR_UNLOCK 0x8 /* SCLR unlock register */
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+#define SLCR_PS_RST_CTRL_OFFSET 0x200 /* PS Software Reset Control */
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+#define SLCR_REBOOT_STATUS 0x258 /* PS Reboot Status */
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+
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void __iomem *zynq_slcr_base;
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+/**
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+ * zynq_slcr_system_reset - Reset the entire system.
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+ */
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+void zynq_slcr_system_reset(void)
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+{
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+ u32 reboot;
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+
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+ /*
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+ * Unlock the SLCR then reset the system.
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+ * Note that this seems to require raw i/o
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+ * functions or there's a lockup?
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+ */
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+ writel(SLCR_UNLOCK_MAGIC, zynq_slcr_base + SLCR_UNLOCK);
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+
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+ /*
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+ * Clear 0x0F000000 bits of reboot status register to workaround
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+ * the FSBL not loading the bitstream after soft-reboot
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+ * This is a temporary solution until we know more.
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+ */
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+ reboot = readl(zynq_slcr_base + SLCR_REBOOT_STATUS);
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+ writel(reboot & 0xF0FFFFFF, zynq_slcr_base + SLCR_REBOOT_STATUS);
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+ writel(1, zynq_slcr_base + SLCR_PS_RST_CTRL_OFFSET);
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+}
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+
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/**
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* zynq_slcr_init
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* Returns 0 on success, negative errno otherwise.
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