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@@ -103,6 +103,13 @@
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#define ADSP1_START_SHIFT 0 /* DSP1_START */
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#define ADSP1_START_WIDTH 1 /* DSP1_START */
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+/*
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+ * ADSP1 Control 31
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+ */
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+#define ADSP1_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
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+#define ADSP1_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
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+#define ADSP1_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
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+
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#define ADSP2_CONTROL 0
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#define ADSP2_CLOCKING 1
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#define ADSP2_STATUS1 4
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@@ -806,12 +813,38 @@ int wm_adsp1_event(struct snd_soc_dapm_widget *w,
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struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
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struct wm_adsp *dsp = &dsps[w->shift];
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int ret;
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+ int val;
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switch (event) {
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case SND_SOC_DAPM_POST_PMU:
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regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
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ADSP1_SYS_ENA, ADSP1_SYS_ENA);
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+ /*
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+ * For simplicity set the DSP clock rate to be the
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+ * SYSCLK rate rather than making it configurable.
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+ */
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+ if(dsp->sysclk_reg) {
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+ ret = regmap_read(dsp->regmap, dsp->sysclk_reg, &val);
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+ if (ret != 0) {
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+ adsp_err(dsp, "Failed to read SYSCLK state: %d\n",
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+ ret);
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+ return ret;
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+ }
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+
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+ val = (val & dsp->sysclk_mask)
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+ >> dsp->sysclk_shift;
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+
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+ ret = regmap_update_bits(dsp->regmap,
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+ dsp->base + ADSP1_CONTROL_31,
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+ ADSP1_CLK_SEL_MASK, val);
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+ if (ret != 0) {
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+ adsp_err(dsp, "Failed to set clock rate: %d\n",
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+ ret);
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+ return ret;
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+ }
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+ }
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+
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ret = wm_adsp_load(dsp);
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if (ret != 0)
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goto err;
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