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@@ -32,6 +32,11 @@
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#include "base.h"
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#include "debug.h"
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+
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+/******************\
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+* Helper functions *
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+\******************/
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+
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/*
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* Check if a register write has been completed
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*/
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@@ -53,146 +58,165 @@ int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val,
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return (i <= 0) ? -EAGAIN : 0;
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}
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+
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+/*************************\
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+* Clock related functions *
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+\*************************/
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+
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/**
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- * ath5k_hw_write_ofdm_timings - set OFDM timings on AR5212
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- *
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- * @ah: the &struct ath5k_hw
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- * @channel: the currently set channel upon reset
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+ * ath5k_hw_htoclock - Translate usec to hw clock units
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*
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- * Write the delta slope coefficient (used on pilot tracking ?) for OFDM
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- * operation on the AR5212 upon reset. This is a helper for ath5k_hw_reset().
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- *
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- * Since delta slope is floating point we split it on its exponent and
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- * mantissa and provide these values on hw.
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- *
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- * For more infos i think this patent is related
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- * http://www.freepatentsonline.com/7184495.html
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+ * @ah: The &struct ath5k_hw
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+ * @usec: value in microseconds
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*/
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-static inline int ath5k_hw_write_ofdm_timings(struct ath5k_hw *ah,
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- struct ieee80211_channel *channel)
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+unsigned int ath5k_hw_htoclock(struct ath5k_hw *ah, unsigned int usec)
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{
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- /* Get exponent and mantissa and set it */
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- u32 coef_scaled, coef_exp, coef_man,
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- ds_coef_exp, ds_coef_man, clock;
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-
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- BUG_ON(!(ah->ah_version == AR5K_AR5212) ||
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- !(channel->hw_value & CHANNEL_OFDM));
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-
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- /* Get coefficient
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- * ALGO: coef = (5 * clock / carrier_freq) / 2
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- * we scale coef by shifting clock value by 24 for
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- * better precision since we use integers */
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- /* TODO: Half/quarter rate */
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- clock = (channel->hw_value & CHANNEL_TURBO) ? 80 : 40;
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- coef_scaled = ((5 * (clock << 24)) / 2) / channel->center_freq;
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-
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- /* Get exponent
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- * ALGO: coef_exp = 14 - highest set bit position */
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- coef_exp = ilog2(coef_scaled);
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-
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- /* Doesn't make sense if it's zero*/
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- if (!coef_scaled || !coef_exp)
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- return -EINVAL;
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-
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- /* Note: we've shifted coef_scaled by 24 */
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- coef_exp = 14 - (coef_exp - 24);
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+ struct ath_common *common = ath5k_hw_common(ah);
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+ return usec * common->clockrate;
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+}
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+/**
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+ * ath5k_hw_clocktoh - Translate hw clock units to usec
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+ * @clock: value in hw clock units
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+ */
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+unsigned int ath5k_hw_clocktoh(struct ath5k_hw *ah, unsigned int clock)
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+{
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+ struct ath_common *common = ath5k_hw_common(ah);
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+ return clock / common->clockrate;
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+}
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- /* Get mantissa (significant digits)
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- * ALGO: coef_mant = floor(coef_scaled* 2^coef_exp+0.5) */
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- coef_man = coef_scaled +
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- (1 << (24 - coef_exp - 1));
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+/**
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+ * ath5k_hw_set_clockrate - Set common->clockrate for the current channel
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+ *
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+ * @ah: The &struct ath5k_hw
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+ */
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+void ath5k_hw_set_clockrate(struct ath5k_hw *ah)
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+{
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+ struct ieee80211_channel *channel = ah->ah_current_channel;
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+ struct ath_common *common = ath5k_hw_common(ah);
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+ int clock;
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- /* Calculate delta slope coefficient exponent
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- * and mantissa (remove scaling) and set them on hw */
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- ds_coef_man = coef_man >> (24 - coef_exp);
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- ds_coef_exp = coef_exp - 16;
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+ if (channel->hw_value & CHANNEL_5GHZ)
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+ clock = 40; /* 802.11a */
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+ else if (channel->hw_value & CHANNEL_CCK)
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+ clock = 22; /* 802.11b */
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+ else
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+ clock = 44; /* 802.11g */
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- AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3,
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- AR5K_PHY_TIMING_3_DSC_MAN, ds_coef_man);
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- AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3,
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- AR5K_PHY_TIMING_3_DSC_EXP, ds_coef_exp);
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+ /* Clock rate in turbo modes is twice the normal rate */
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+ if (channel->hw_value & CHANNEL_TURBO)
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+ clock *= 2;
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- return 0;
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+ common->clockrate = clock;
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}
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-
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/*
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- * index into rates for control rates, we can set it up like this because
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- * this is only used for AR5212 and we know it supports G mode
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- */
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-static const unsigned int control_rates[] =
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- { 0, 1, 1, 1, 4, 4, 6, 6, 8, 8, 8, 8 };
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-
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-/**
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- * ath5k_hw_write_rate_duration - fill rate code to duration table
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- *
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- * @ah: the &struct ath5k_hw
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- * @mode: one of enum ath5k_driver_mode
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- *
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- * Write the rate code to duration table upon hw reset. This is a helper for
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- * ath5k_hw_reset(). It seems all this is doing is setting an ACK timeout on
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- * the hardware, based on current mode, for each rate. The rates which are
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- * capable of short preamble (802.11b rates 2Mbps, 5.5Mbps, and 11Mbps) have
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- * different rate code so we write their value twice (one for long preample
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- * and one for short).
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+ * If there is an external 32KHz crystal available, use it
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+ * as ref. clock instead of 32/40MHz clock and baseband clocks
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+ * to save power during sleep or restore normal 32/40MHz
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+ * operation.
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*
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- * Note: Band doesn't matter here, if we set the values for OFDM it works
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- * on both a and g modes. So all we have to do is set values for all g rates
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- * that include all OFDM and CCK rates. If we operate in turbo or xr/half/
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- * quarter rate mode, we need to use another set of bitrates (that's why we
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- * need the mode parameter) but we don't handle these proprietary modes yet.
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+ * XXX: When operating on 32KHz certain PHY registers (27 - 31,
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+ * 123 - 127) require delay on access.
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*/
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-static inline void ath5k_hw_write_rate_duration(struct ath5k_hw *ah,
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- unsigned int mode)
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+static void ath5k_hw_set_sleep_clock(struct ath5k_hw *ah, bool enable)
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{
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- struct ath5k_softc *sc = ah->ah_sc;
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- struct ieee80211_rate *rate;
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- unsigned int i;
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+ struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
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+ u32 scal, spending, usec32;
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+
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+ /* Only set 32KHz settings if we have an external
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+ * 32KHz crystal present */
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+ if ((AR5K_EEPROM_HAS32KHZCRYSTAL(ee->ee_misc1) ||
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+ AR5K_EEPROM_HAS32KHZCRYSTAL_OLD(ee->ee_misc1)) &&
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+ enable) {
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+
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+ /* 1 usec/cycle */
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+ AR5K_REG_WRITE_BITS(ah, AR5K_USEC_5211, AR5K_USEC_32, 1);
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+ /* Set up tsf increment on each cycle */
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+ AR5K_REG_WRITE_BITS(ah, AR5K_TSF_PARM, AR5K_TSF_PARM_INC, 61);
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+
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+ /* Set baseband sleep control registers
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+ * and sleep control rate */
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+ ath5k_hw_reg_write(ah, 0x1f, AR5K_PHY_SCR);
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+
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+ if ((ah->ah_radio == AR5K_RF5112) ||
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+ (ah->ah_radio == AR5K_RF5413) ||
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+ (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
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+ spending = 0x14;
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+ else
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+ spending = 0x18;
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+ ath5k_hw_reg_write(ah, spending, AR5K_PHY_SPENDING);
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+
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+ if ((ah->ah_radio == AR5K_RF5112) ||
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+ (ah->ah_radio == AR5K_RF5413) ||
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+ (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) {
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+ ath5k_hw_reg_write(ah, 0x26, AR5K_PHY_SLMT);
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+ ath5k_hw_reg_write(ah, 0x0d, AR5K_PHY_SCAL);
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+ ath5k_hw_reg_write(ah, 0x07, AR5K_PHY_SCLOCK);
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+ ath5k_hw_reg_write(ah, 0x3f, AR5K_PHY_SDELAY);
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+ AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,
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+ AR5K_PCICFG_SLEEP_CLOCK_RATE, 0x02);
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+ } else {
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+ ath5k_hw_reg_write(ah, 0x0a, AR5K_PHY_SLMT);
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+ ath5k_hw_reg_write(ah, 0x0c, AR5K_PHY_SCAL);
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+ ath5k_hw_reg_write(ah, 0x03, AR5K_PHY_SCLOCK);
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+ ath5k_hw_reg_write(ah, 0x20, AR5K_PHY_SDELAY);
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+ AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,
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+ AR5K_PCICFG_SLEEP_CLOCK_RATE, 0x03);
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+ }
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- /* Write rate duration table */
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- for (i = 0; i < sc->sbands[IEEE80211_BAND_2GHZ].n_bitrates; i++) {
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- u32 reg;
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- u16 tx_time;
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+ /* Enable sleep clock operation */
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+ AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG,
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+ AR5K_PCICFG_SLEEP_CLOCK_EN);
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- rate = &sc->sbands[IEEE80211_BAND_2GHZ].bitrates[control_rates[i]];
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+ } else {
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- /* Set ACK timeout */
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- reg = AR5K_RATE_DUR(rate->hw_value);
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+ /* Disable sleep clock operation and
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+ * restore default parameters */
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+ AR5K_REG_DISABLE_BITS(ah, AR5K_PCICFG,
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+ AR5K_PCICFG_SLEEP_CLOCK_EN);
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- /* An ACK frame consists of 10 bytes. If you add the FCS,
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- * which ieee80211_generic_frame_duration() adds,
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- * its 14 bytes. Note we use the control rate and not the
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- * actual rate for this rate. See mac80211 tx.c
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- * ieee80211_duration() for a brief description of
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- * what rate we should choose to TX ACKs. */
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- tx_time = le16_to_cpu(ieee80211_generic_frame_duration(sc->hw,
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- NULL, 10, rate));
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+ AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,
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+ AR5K_PCICFG_SLEEP_CLOCK_RATE, 0);
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- ath5k_hw_reg_write(ah, tx_time, reg);
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+ ath5k_hw_reg_write(ah, 0x1f, AR5K_PHY_SCR);
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+ ath5k_hw_reg_write(ah, AR5K_PHY_SLMT_32MHZ, AR5K_PHY_SLMT);
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- if (!(rate->flags & IEEE80211_RATE_SHORT_PREAMBLE))
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- continue;
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+ if (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))
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+ scal = AR5K_PHY_SCAL_32MHZ_2417;
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+ else if (ee->ee_is_hb63)
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+ scal = AR5K_PHY_SCAL_32MHZ_HB63;
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+ else
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+ scal = AR5K_PHY_SCAL_32MHZ;
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+ ath5k_hw_reg_write(ah, scal, AR5K_PHY_SCAL);
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- /*
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- * We're not distinguishing short preamble here,
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- * This is true, all we'll get is a longer value here
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- * which is not necessarilly bad. We could use
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- * export ieee80211_frame_duration() but that needs to be
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- * fixed first to be properly used by mac802111 drivers:
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- *
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- * - remove erp stuff and let the routine figure ofdm
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- * erp rates
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- * - remove passing argument ieee80211_local as
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- * drivers don't have access to it
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- * - move drivers using ieee80211_generic_frame_duration()
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- * to this
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- */
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- ath5k_hw_reg_write(ah, tx_time,
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- reg + (AR5K_SET_SHORT_PREAMBLE << 2));
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+ ath5k_hw_reg_write(ah, AR5K_PHY_SCLOCK_32MHZ, AR5K_PHY_SCLOCK);
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+ ath5k_hw_reg_write(ah, AR5K_PHY_SDELAY_32MHZ, AR5K_PHY_SDELAY);
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+
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+ if ((ah->ah_radio == AR5K_RF5112) ||
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+ (ah->ah_radio == AR5K_RF5413) ||
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+ (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
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+ spending = 0x14;
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+ else
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+ spending = 0x18;
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+ ath5k_hw_reg_write(ah, spending, AR5K_PHY_SPENDING);
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+
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+ if ((ah->ah_radio == AR5K_RF5112) ||
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+ (ah->ah_radio == AR5K_RF5413))
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+ usec32 = 39;
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+ else
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+ usec32 = 31;
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+ AR5K_REG_WRITE_BITS(ah, AR5K_USEC_5211, AR5K_USEC_32, usec32);
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+
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+ AR5K_REG_WRITE_BITS(ah, AR5K_TSF_PARM, AR5K_TSF_PARM_INC, 1);
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}
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}
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+
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+/*********************\
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+* Reset/Sleep control *
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+\*********************/
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+
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/*
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* Reset chipset
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*/
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@@ -522,107 +546,10 @@ int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial)
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return 0;
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}
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-/*
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- * If there is an external 32KHz crystal available, use it
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- * as ref. clock instead of 32/40MHz clock and baseband clocks
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- * to save power during sleep or restore normal 32/40MHz
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- * operation.
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- *
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- * XXX: When operating on 32KHz certain PHY registers (27 - 31,
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- * 123 - 127) require delay on access.
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- */
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-static void ath5k_hw_set_sleep_clock(struct ath5k_hw *ah, bool enable)
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-{
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- struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
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- u32 scal, spending, usec32;
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-
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- /* Only set 32KHz settings if we have an external
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- * 32KHz crystal present */
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- if ((AR5K_EEPROM_HAS32KHZCRYSTAL(ee->ee_misc1) ||
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- AR5K_EEPROM_HAS32KHZCRYSTAL_OLD(ee->ee_misc1)) &&
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- enable) {
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-
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- /* 1 usec/cycle */
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- AR5K_REG_WRITE_BITS(ah, AR5K_USEC_5211, AR5K_USEC_32, 1);
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- /* Set up tsf increment on each cycle */
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- AR5K_REG_WRITE_BITS(ah, AR5K_TSF_PARM, AR5K_TSF_PARM_INC, 61);
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-
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- /* Set baseband sleep control registers
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- * and sleep control rate */
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- ath5k_hw_reg_write(ah, 0x1f, AR5K_PHY_SCR);
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-
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- if ((ah->ah_radio == AR5K_RF5112) ||
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- (ah->ah_radio == AR5K_RF5413) ||
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- (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
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- spending = 0x14;
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- else
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- spending = 0x18;
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- ath5k_hw_reg_write(ah, spending, AR5K_PHY_SPENDING);
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-
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- if ((ah->ah_radio == AR5K_RF5112) ||
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- (ah->ah_radio == AR5K_RF5413) ||
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- (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) {
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- ath5k_hw_reg_write(ah, 0x26, AR5K_PHY_SLMT);
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- ath5k_hw_reg_write(ah, 0x0d, AR5K_PHY_SCAL);
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- ath5k_hw_reg_write(ah, 0x07, AR5K_PHY_SCLOCK);
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- ath5k_hw_reg_write(ah, 0x3f, AR5K_PHY_SDELAY);
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- AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,
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- AR5K_PCICFG_SLEEP_CLOCK_RATE, 0x02);
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- } else {
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- ath5k_hw_reg_write(ah, 0x0a, AR5K_PHY_SLMT);
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- ath5k_hw_reg_write(ah, 0x0c, AR5K_PHY_SCAL);
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- ath5k_hw_reg_write(ah, 0x03, AR5K_PHY_SCLOCK);
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- ath5k_hw_reg_write(ah, 0x20, AR5K_PHY_SDELAY);
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- AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,
|
|
|
- AR5K_PCICFG_SLEEP_CLOCK_RATE, 0x03);
|
|
|
- }
|
|
|
|
|
|
- /* Enable sleep clock operation */
|
|
|
- AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG,
|
|
|
- AR5K_PCICFG_SLEEP_CLOCK_EN);
|
|
|
-
|
|
|
- } else {
|
|
|
-
|
|
|
- /* Disable sleep clock operation and
|
|
|
- * restore default parameters */
|
|
|
- AR5K_REG_DISABLE_BITS(ah, AR5K_PCICFG,
|
|
|
- AR5K_PCICFG_SLEEP_CLOCK_EN);
|
|
|
-
|
|
|
- AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,
|
|
|
- AR5K_PCICFG_SLEEP_CLOCK_RATE, 0);
|
|
|
-
|
|
|
- ath5k_hw_reg_write(ah, 0x1f, AR5K_PHY_SCR);
|
|
|
- ath5k_hw_reg_write(ah, AR5K_PHY_SLMT_32MHZ, AR5K_PHY_SLMT);
|
|
|
-
|
|
|
- if (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))
|
|
|
- scal = AR5K_PHY_SCAL_32MHZ_2417;
|
|
|
- else if (ee->ee_is_hb63)
|
|
|
- scal = AR5K_PHY_SCAL_32MHZ_HB63;
|
|
|
- else
|
|
|
- scal = AR5K_PHY_SCAL_32MHZ;
|
|
|
- ath5k_hw_reg_write(ah, scal, AR5K_PHY_SCAL);
|
|
|
-
|
|
|
- ath5k_hw_reg_write(ah, AR5K_PHY_SCLOCK_32MHZ, AR5K_PHY_SCLOCK);
|
|
|
- ath5k_hw_reg_write(ah, AR5K_PHY_SDELAY_32MHZ, AR5K_PHY_SDELAY);
|
|
|
-
|
|
|
- if ((ah->ah_radio == AR5K_RF5112) ||
|
|
|
- (ah->ah_radio == AR5K_RF5413) ||
|
|
|
- (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
|
|
|
- spending = 0x14;
|
|
|
- else
|
|
|
- spending = 0x18;
|
|
|
- ath5k_hw_reg_write(ah, spending, AR5K_PHY_SPENDING);
|
|
|
-
|
|
|
- if ((ah->ah_radio == AR5K_RF5112) ||
|
|
|
- (ah->ah_radio == AR5K_RF5413))
|
|
|
- usec32 = 39;
|
|
|
- else
|
|
|
- usec32 = 31;
|
|
|
- AR5K_REG_WRITE_BITS(ah, AR5K_USEC_5211, AR5K_USEC_32, usec32);
|
|
|
-
|
|
|
- AR5K_REG_WRITE_BITS(ah, AR5K_TSF_PARM, AR5K_TSF_PARM_INC, 1);
|
|
|
- }
|
|
|
-}
|
|
|
+/**************************************\
|
|
|
+* Post-initvals register modifications *
|
|
|
+\**************************************/
|
|
|
|
|
|
/* TODO: Half/Quarter rate */
|
|
|
static void ath5k_hw_tweak_initval_settings(struct ath5k_hw *ah,
|
|
@@ -705,7 +632,8 @@ static void ath5k_hw_tweak_initval_settings(struct ath5k_hw *ah,
|
|
|
ath5k_hw_reg_write(ah, data, AR5K_PHY_FRAME_CTL);
|
|
|
}
|
|
|
|
|
|
- if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
|
|
|
+ if ((ah->ah_radio == AR5K_RF5112) &&
|
|
|
+ (ah->ah_mac_srev < AR5K_SREV_AR5211)) {
|
|
|
u32 usec_reg;
|
|
|
/* 5311 has different tx/rx latency masks
|
|
|
* from 5211, since we deal 5311 the same
|
|
@@ -734,6 +662,10 @@ static void ath5k_hw_commit_eeprom_settings(struct ath5k_hw *ah,
|
|
|
struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
|
|
|
s16 cck_ofdm_pwr_delta;
|
|
|
|
|
|
+ /* TODO: Add support for AR5210 EEPROM */
|
|
|
+ if (ah->ah_version == AR5K_AR5210)
|
|
|
+ return;
|
|
|
+
|
|
|
/* Adjust power delta for channel 14 */
|
|
|
if (channel->center_freq == 2484)
|
|
|
cck_ofdm_pwr_delta =
|
|
@@ -870,15 +802,16 @@ static void ath5k_hw_commit_eeprom_settings(struct ath5k_hw *ah,
|
|
|
ath5k_hw_reg_write(ah, 0, AR5K_PHY_HEAVY_CLIP_ENABLE);
|
|
|
}
|
|
|
|
|
|
-/*
|
|
|
- * Main reset function
|
|
|
- */
|
|
|
+
|
|
|
+/*********************\
|
|
|
+* Main reset function *
|
|
|
+\*********************/
|
|
|
+
|
|
|
int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
|
|
|
struct ieee80211_channel *channel, bool change_channel)
|
|
|
{
|
|
|
struct ath_common *common = ath5k_hw_common(ah);
|
|
|
u32 s_seq[10], s_led[3], staid1_flags, tsf_up, tsf_lo;
|
|
|
- u32 phy_tst1;
|
|
|
u8 mode, freq, ee_mode;
|
|
|
int i, ret;
|
|
|
|
|
@@ -1026,93 +959,15 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
|
|
|
return ret;
|
|
|
|
|
|
/*
|
|
|
- * 5211/5212 Specific
|
|
|
+ * Tweak initval settings for revised
|
|
|
+ * chipsets and add some more config
|
|
|
+ * bits
|
|
|
*/
|
|
|
- if (ah->ah_version != AR5K_AR5210) {
|
|
|
-
|
|
|
- /*
|
|
|
- * Write initial RF gain settings
|
|
|
- * This should work for both 5111/5112
|
|
|
- */
|
|
|
- ret = ath5k_hw_rfgain_init(ah, freq);
|
|
|
- if (ret)
|
|
|
- return ret;
|
|
|
-
|
|
|
- mdelay(1);
|
|
|
-
|
|
|
- /*
|
|
|
- * Tweak initval settings for revised
|
|
|
- * chipsets and add some more config
|
|
|
- * bits
|
|
|
- */
|
|
|
- ath5k_hw_tweak_initval_settings(ah, channel);
|
|
|
-
|
|
|
- /*
|
|
|
- * Set TX power
|
|
|
- */
|
|
|
- ret = ath5k_hw_txpower(ah, channel, ee_mode,
|
|
|
- ah->ah_txpower.txp_max_pwr / 2);
|
|
|
- if (ret)
|
|
|
- return ret;
|
|
|
-
|
|
|
- /* Write rate duration table only on AR5212 and if
|
|
|
- * virtual interface has already been brought up
|
|
|
- * XXX: rethink this after new mode changes to
|
|
|
- * mac80211 are integrated */
|
|
|
- if (ah->ah_version == AR5K_AR5212 &&
|
|
|
- ah->ah_sc->nvifs)
|
|
|
- ath5k_hw_write_rate_duration(ah, mode);
|
|
|
-
|
|
|
- /*
|
|
|
- * Write RF buffer
|
|
|
- */
|
|
|
- ret = ath5k_hw_rfregs_init(ah, channel, mode);
|
|
|
- if (ret)
|
|
|
- return ret;
|
|
|
-
|
|
|
-
|
|
|
- /* Write OFDM timings on 5212*/
|
|
|
- if (ah->ah_version == AR5K_AR5212 &&
|
|
|
- channel->hw_value & CHANNEL_OFDM) {
|
|
|
+ ath5k_hw_tweak_initval_settings(ah, channel);
|
|
|
|
|
|
- ret = ath5k_hw_write_ofdm_timings(ah, channel);
|
|
|
- if (ret)
|
|
|
- return ret;
|
|
|
+ /* Commit values from EEPROM */
|
|
|
+ ath5k_hw_commit_eeprom_settings(ah, channel, ee_mode);
|
|
|
|
|
|
- /* Spur info is available only from EEPROM versions
|
|
|
- * greater than 5.3, but the EEPROM routines will use
|
|
|
- * static values for older versions */
|
|
|
- if (ah->ah_mac_srev >= AR5K_SREV_AR5424)
|
|
|
- ath5k_hw_set_spur_mitigation_filter(ah,
|
|
|
- channel);
|
|
|
- }
|
|
|
-
|
|
|
- /*Enable/disable 802.11b mode on 5111
|
|
|
- (enable 2111 frequency converter + CCK)*/
|
|
|
- if (ah->ah_radio == AR5K_RF5111) {
|
|
|
- if (mode == AR5K_MODE_11B)
|
|
|
- AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG,
|
|
|
- AR5K_TXCFG_B_MODE);
|
|
|
- else
|
|
|
- AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG,
|
|
|
- AR5K_TXCFG_B_MODE);
|
|
|
- }
|
|
|
-
|
|
|
- /* Commit values from EEPROM */
|
|
|
- ath5k_hw_commit_eeprom_settings(ah, channel, ee_mode);
|
|
|
-
|
|
|
- } else {
|
|
|
- /*
|
|
|
- * For 5210 we do all initialization using
|
|
|
- * initvals, so we don't have to modify
|
|
|
- * any settings (5210 also only supports
|
|
|
- * a/aturbo modes)
|
|
|
- */
|
|
|
- mdelay(1);
|
|
|
- /* Disable phy and wait */
|
|
|
- ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
|
|
|
- mdelay(1);
|
|
|
- }
|
|
|
|
|
|
/*
|
|
|
* Restore saved values
|
|
@@ -1156,193 +1011,38 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
|
|
|
|
|
|
|
|
|
/*
|
|
|
- * Configure PCU
|
|
|
+ * Initialize PCU
|
|
|
*/
|
|
|
-
|
|
|
- /* Restore bssid and bssid mask */
|
|
|
- ath5k_hw_set_bssid(ah);
|
|
|
-
|
|
|
- /* Set PCU config */
|
|
|
- ath5k_hw_set_opmode(ah, op_mode);
|
|
|
+ ath5k_hw_pcu_init(ah, op_mode, mode);
|
|
|
|
|
|
/* Clear any pending interrupts
|
|
|
* PISR/SISR Not available on 5210 */
|
|
|
if (ah->ah_version != AR5K_AR5210)
|
|
|
ath5k_hw_reg_write(ah, 0xffffffff, AR5K_PISR);
|
|
|
|
|
|
- /* Set RSSI/BRSSI thresholds
|
|
|
- *
|
|
|
- * Note: If we decide to set this value
|
|
|
- * dynamically, keep in mind that when AR5K_RSSI_THR
|
|
|
- * register is read, it might return 0x40 if we haven't
|
|
|
- * written anything to it. Also, BMISS RSSI threshold is zeroed.
|
|
|
- * So doing a save/restore procedure here isn't the right
|
|
|
- * choice. Instead, store it in ath5k_hw */
|
|
|
- ath5k_hw_reg_write(ah, (AR5K_TUNE_RSSI_THRES |
|
|
|
- AR5K_TUNE_BMISS_THRES <<
|
|
|
- AR5K_RSSI_THR_BMISS_S),
|
|
|
- AR5K_RSSI_THR);
|
|
|
-
|
|
|
- /* MIC QoS support */
|
|
|
- if (ah->ah_mac_srev >= AR5K_SREV_AR2413) {
|
|
|
- ath5k_hw_reg_write(ah, 0x000100aa, AR5K_MIC_QOS_CTL);
|
|
|
- ath5k_hw_reg_write(ah, 0x00003210, AR5K_MIC_QOS_SEL);
|
|
|
- }
|
|
|
-
|
|
|
- /* QoS NOACK Policy */
|
|
|
- if (ah->ah_version == AR5K_AR5212) {
|
|
|
- ath5k_hw_reg_write(ah,
|
|
|
- AR5K_REG_SM(2, AR5K_QOS_NOACK_2BIT_VALUES) |
|
|
|
- AR5K_REG_SM(5, AR5K_QOS_NOACK_BIT_OFFSET) |
|
|
|
- AR5K_REG_SM(0, AR5K_QOS_NOACK_BYTE_OFFSET),
|
|
|
- AR5K_QOS_NOACK);
|
|
|
- }
|
|
|
-
|
|
|
-
|
|
|
/*
|
|
|
- * Configure PHY
|
|
|
+ * Initialize PHY
|
|
|
*/
|
|
|
-
|
|
|
- /* Set channel on PHY */
|
|
|
- ret = ath5k_hw_channel(ah, channel);
|
|
|
- if (ret)
|
|
|
+ ret = ath5k_hw_phy_init(ah, channel, mode, ee_mode, freq);
|
|
|
+ if (ret) {
|
|
|
+ ATH5K_ERR(ah->ah_sc,
|
|
|
+ "failed to initialize PHY (%i) !\n", ret);
|
|
|
return ret;
|
|
|
-
|
|
|
- /*
|
|
|
- * Enable the PHY and wait until completion
|
|
|
- * This includes BaseBand and Synthesizer
|
|
|
- * activation.
|
|
|
- */
|
|
|
- ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
|
|
|
-
|
|
|
- /*
|
|
|
- * On 5211+ read activation -> rx delay
|
|
|
- * and use it.
|
|
|
- *
|
|
|
- * TODO: Half/quarter rate support
|
|
|
- */
|
|
|
- if (ah->ah_version != AR5K_AR5210) {
|
|
|
- u32 delay;
|
|
|
- delay = ath5k_hw_reg_read(ah, AR5K_PHY_RX_DELAY) &
|
|
|
- AR5K_PHY_RX_DELAY_M;
|
|
|
- delay = (channel->hw_value & CHANNEL_CCK) ?
|
|
|
- ((delay << 2) / 22) : (delay / 10);
|
|
|
-
|
|
|
- udelay(100 + (2 * delay));
|
|
|
- } else {
|
|
|
- mdelay(1);
|
|
|
- }
|
|
|
-
|
|
|
- /*
|
|
|
- * Perform ADC test to see if baseband is ready
|
|
|
- * Set TX hold and check ADC test register
|
|
|
- */
|
|
|
- phy_tst1 = ath5k_hw_reg_read(ah, AR5K_PHY_TST1);
|
|
|
- ath5k_hw_reg_write(ah, AR5K_PHY_TST1_TXHOLD, AR5K_PHY_TST1);
|
|
|
- for (i = 0; i <= 20; i++) {
|
|
|
- if (!(ath5k_hw_reg_read(ah, AR5K_PHY_ADC_TEST) & 0x10))
|
|
|
- break;
|
|
|
- udelay(200);
|
|
|
- }
|
|
|
- ath5k_hw_reg_write(ah, phy_tst1, AR5K_PHY_TST1);
|
|
|
-
|
|
|
- /*
|
|
|
- * Start automatic gain control calibration
|
|
|
- *
|
|
|
- * During AGC calibration RX path is re-routed to
|
|
|
- * a power detector so we don't receive anything.
|
|
|
- *
|
|
|
- * This method is used to calibrate some static offsets
|
|
|
- * used together with on-the fly I/Q calibration (the
|
|
|
- * one performed via ath5k_hw_phy_calibrate), which doesn't
|
|
|
- * interrupt rx path.
|
|
|
- *
|
|
|
- * While rx path is re-routed to the power detector we also
|
|
|
- * start a noise floor calibration to measure the
|
|
|
- * card's noise floor (the noise we measure when we are not
|
|
|
- * transmitting or receiving anything).
|
|
|
- *
|
|
|
- * If we are in a noisy environment, AGC calibration may time
|
|
|
- * out and/or noise floor calibration might timeout.
|
|
|
- */
|
|
|
- AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
|
|
|
- AR5K_PHY_AGCCTL_CAL | AR5K_PHY_AGCCTL_NF);
|
|
|
-
|
|
|
- /* At the same time start I/Q calibration for QAM constellation
|
|
|
- * -no need for CCK- */
|
|
|
- ah->ah_calibration = false;
|
|
|
- if (!(mode == AR5K_MODE_11B)) {
|
|
|
- ah->ah_calibration = true;
|
|
|
- AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ,
|
|
|
- AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15);
|
|
|
- AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
|
|
|
- AR5K_PHY_IQ_RUN);
|
|
|
- }
|
|
|
-
|
|
|
- /* Wait for gain calibration to finish (we check for I/Q calibration
|
|
|
- * during ath5k_phy_calibrate) */
|
|
|
- if (ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
|
|
|
- AR5K_PHY_AGCCTL_CAL, 0, false)) {
|
|
|
- ATH5K_ERR(ah->ah_sc, "gain calibration timeout (%uMHz)\n",
|
|
|
- channel->center_freq);
|
|
|
}
|
|
|
|
|
|
- /* Restore antenna mode */
|
|
|
- ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode);
|
|
|
-
|
|
|
- /* Restore slot time and ACK timeouts */
|
|
|
- if (ah->ah_coverage_class > 0)
|
|
|
- ath5k_hw_set_coverage_class(ah, ah->ah_coverage_class);
|
|
|
-
|
|
|
/*
|
|
|
* Configure QCUs/DCUs
|
|
|
*/
|
|
|
+ ret = ath5k_hw_init_queues(ah);
|
|
|
+ if (ret)
|
|
|
+ return ret;
|
|
|
|
|
|
- /* TODO: HW Compression support for data queues */
|
|
|
- /* TODO: Burst prefetch for data queues */
|
|
|
-
|
|
|
- /*
|
|
|
- * Reset queues and start beacon timers at the end of the reset routine
|
|
|
- * This also sets QCU mask on each DCU for 1:1 qcu to dcu mapping
|
|
|
- * Note: If we want we can assign multiple qcus on one dcu.
|
|
|
- */
|
|
|
- for (i = 0; i < ah->ah_capabilities.cap_queues.q_tx_num; i++) {
|
|
|
- ret = ath5k_hw_reset_tx_queue(ah, i);
|
|
|
- if (ret) {
|
|
|
- ATH5K_ERR(ah->ah_sc,
|
|
|
- "failed to reset TX queue #%d\n", i);
|
|
|
- return ret;
|
|
|
- }
|
|
|
- }
|
|
|
-
|
|
|
-
|
|
|
- /*
|
|
|
- * Configure DMA/Interrupts
|
|
|
- */
|
|
|
|
|
|
/*
|
|
|
- * Set Rx/Tx DMA Configuration
|
|
|
- *
|
|
|
- * Set standard DMA size (128). Note that
|
|
|
- * a DMA size of 512 causes rx overruns and tx errors
|
|
|
- * on pci-e cards (tested on 5424 but since rx overruns
|
|
|
- * also occur on 5416/5418 with madwifi we set 128
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- * for all PCI-E cards to be safe).
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- *
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- * XXX: need to check 5210 for this
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- * TODO: Check out tx triger level, it's always 64 on dumps but I
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- * guess we can tweak it and see how it goes ;-)
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+ * Initialize DMA/Interrupts
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*/
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- if (ah->ah_version != AR5K_AR5210) {
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- AR5K_REG_WRITE_BITS(ah, AR5K_TXCFG,
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- AR5K_TXCFG_SDMAMR, AR5K_DMASIZE_128B);
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- AR5K_REG_WRITE_BITS(ah, AR5K_RXCFG,
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- AR5K_RXCFG_SDMAMW, AR5K_DMASIZE_128B);
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- }
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+ ath5k_hw_dma_init(ah);
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- /* Pre-enable interrupts on 5211/5212*/
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- if (ah->ah_version != AR5K_AR5210)
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- ath5k_hw_set_imr(ah, ah->ah_imr);
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/* Enable 32KHz clock function for AR5212+ chips
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* Set clocks to 32KHz operation and use an
|