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@@ -3525,6 +3525,41 @@ void intel_init_clock_gating(struct drm_device *dev)
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dev_priv->display.init_pch_clock_gating(dev);
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}
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+static void gen6_sanitize_pm(struct drm_device *dev)
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+{
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+ struct drm_i915_private *dev_priv = dev->dev_private;
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+ u32 limits, delay, old;
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+
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+ gen6_gt_force_wake_get(dev_priv);
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+
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+ old = limits = I915_READ(GEN6_RP_INTERRUPT_LIMITS);
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+ /* Make sure we continue to get interrupts
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+ * until we hit the minimum or maximum frequencies.
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+ */
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+ limits &= ~(0x3f << 16 | 0x3f << 24);
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+ delay = dev_priv->cur_delay;
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+ if (delay < dev_priv->max_delay)
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+ limits |= (dev_priv->max_delay & 0x3f) << 24;
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+ if (delay > dev_priv->min_delay)
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+ limits |= (dev_priv->min_delay & 0x3f) << 16;
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+
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+ if (old != limits) {
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+ DRM_ERROR("Power management discrepancy: GEN6_RP_INTERRUPT_LIMITS expected %08x, was %08x\n",
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+ limits, old);
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+ I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
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+ }
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+
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+ gen6_gt_force_wake_put(dev_priv);
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+}
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+
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+void intel_sanitize_pm(struct drm_device *dev)
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+{
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+ struct drm_i915_private *dev_priv = dev->dev_private;
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+
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+ if (dev_priv->display.sanitize_pm)
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+ dev_priv->display.sanitize_pm(dev);
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+}
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+
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/* Set up chip specific power management-related functions */
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void intel_init_pm(struct drm_device *dev)
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{
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@@ -3607,6 +3642,7 @@ void intel_init_pm(struct drm_device *dev)
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dev_priv->display.update_wm = NULL;
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}
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dev_priv->display.init_clock_gating = gen6_init_clock_gating;
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+ dev_priv->display.sanitize_pm = gen6_sanitize_pm;
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} else if (IS_IVYBRIDGE(dev)) {
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/* FIXME: detect B0+ stepping and use auto training */
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if (SNB_READ_WM0_LATENCY()) {
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@@ -3618,6 +3654,7 @@ void intel_init_pm(struct drm_device *dev)
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dev_priv->display.update_wm = NULL;
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}
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dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
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+ dev_priv->display.sanitize_pm = gen6_sanitize_pm;
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} else
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dev_priv->display.update_wm = NULL;
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} else if (IS_VALLEYVIEW(dev)) {
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