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@@ -1161,8 +1161,8 @@ void bnx2x_sp_event(struct bnx2x_fastpath *fp,
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break;
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}
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- bp->spq_left++;
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-
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+ smp_mb__before_atomic_inc();
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+ atomic_inc(&bp->spq_left);
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/* push the change in fp->state and towards the memory */
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smp_wmb();
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@@ -2432,7 +2432,7 @@ int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
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spin_lock_bh(&bp->spq_lock);
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- if (!bp->spq_left) {
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+ if (!atomic_read(&bp->spq_left)) {
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BNX2X_ERR("BUG! SPQ ring full!\n");
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spin_unlock_bh(&bp->spq_lock);
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bnx2x_panic();
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@@ -2472,7 +2472,7 @@ int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
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* somewhere between the spin_lock and spin_unlock. Thus no
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* more explict memory barrier is needed.
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*/
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- bp->spq_left--;
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+ atomic_dec(&bp->spq_left);
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DP(BNX2X_MSG_SP/*NETIF_MSG_TIMER*/,
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"SPQE[%x] (%x:%x) command %d hw_cid %x data (%x:%x) "
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@@ -2480,7 +2480,7 @@ int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
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bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
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(u32)(U64_LO(bp->spq_mapping) +
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(void *)bp->spq_prod_bd - (void *)bp->spq), command,
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- HW_CID(bp, cid), data_hi, data_lo, type, bp->spq_left);
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+ HW_CID(bp, cid), data_hi, data_lo, type, atomic_read(&bp->spq_left));
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bnx2x_sp_prod_update(bp);
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spin_unlock_bh(&bp->spq_lock);
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@@ -3290,7 +3290,7 @@ static void bnx2x_eq_int(struct bnx2x *bp)
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sw_prod = bp->eq_prod;
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DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->spq_left %u\n",
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- hw_cons, sw_cons, bp->spq_left);
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+ hw_cons, sw_cons, atomic_read(&bp->spq_left));
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for (; sw_cons != hw_cons;
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sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
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@@ -3360,7 +3360,8 @@ next_spqe:
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spqe_cnt++;
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} /* for */
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- bp->spq_left++;
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+ smp_mb__before_atomic_inc();
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+ atomic_add(spqe_cnt, &bp->spq_left);
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bp->eq_cons = sw_cons;
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bp->eq_prod = sw_prod;
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@@ -3737,8 +3738,8 @@ void bnx2x_update_coalesce(struct bnx2x *bp)
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static void bnx2x_init_sp_ring(struct bnx2x *bp)
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{
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spin_lock_init(&bp->spq_lock);
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+ atomic_set(&bp->spq_left, MAX_SPQ_PENDING);
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- bp->spq_left = MAX_SPQ_PENDING;
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bp->spq_prod_idx = 0;
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bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
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bp->spq_prod_bd = bp->spq;
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