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@@ -1013,7 +1013,7 @@ void bnx2x_int_enable(struct bnx2x *bp)
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if (CHIP_IS_E1H(bp)) {
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/* init leading/trailing edge */
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- if (IS_E1HMF(bp)) {
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+ if (IS_MF(bp)) {
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val = (0xee0f | (1 << (BP_E1HVN(bp) + 4)));
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if (bp->port.pmf)
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/* enable nig and gpio3 attention */
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@@ -1792,7 +1792,7 @@ static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
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{
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if (CHIP_REV_IS_SLOW(bp))
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return CMNG_FNS_NONE;
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- if (IS_E1HMF(bp))
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+ if (IS_MF(bp))
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return CMNG_FNS_MINMAX;
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return CMNG_FNS_NONE;
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@@ -1906,7 +1906,7 @@ static void bnx2x_link_attn(struct bnx2x *bp)
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if (prev_link_status != bp->link_vars.link_status)
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bnx2x_link_report(bp);
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- if (IS_E1HMF(bp)) {
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+ if (IS_MF(bp)) {
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int port = BP_PORT(bp);
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int func;
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int vn;
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@@ -2160,7 +2160,7 @@ static inline u16 bnx2x_get_cl_flags(struct bnx2x *bp,
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/* calculate queue flags */
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flags |= QUEUE_FLG_CACHE_ALIGN;
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flags |= QUEUE_FLG_HC;
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- flags |= IS_E1HMF(bp) ? QUEUE_FLG_OV : 0;
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+ flags |= IS_MF(bp) ? QUEUE_FLG_OV : 0;
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#ifdef BCM_VLAN
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flags |= QUEUE_FLG_VLAN;
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@@ -2262,7 +2262,7 @@ void bnx2x_pf_init(struct bnx2x *bp)
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/* pf specific setups */
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if (!CHIP_IS_E1(bp))
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- storm_memset_ov(bp, bp->e1hov, BP_FUNC(bp));
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+ storm_memset_ov(bp, bp->mf_ov, BP_FUNC(bp));
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/* function setup flags */
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flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
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@@ -3855,13 +3855,13 @@ static void bnx2x_init_internal_common(struct bnx2x *bp)
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/* xstorm needs to know whether to add ovlan to packets or not,
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* in switch-independent we'll write 0 to here... */
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REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNCTION_MODE_OFFSET,
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- bp->e1hmf);
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+ bp->mf_mode);
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REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNCTION_MODE_OFFSET,
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- bp->e1hmf);
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+ bp->mf_mode);
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REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNCTION_MODE_OFFSET,
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- bp->e1hmf);
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+ bp->mf_mode);
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REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNCTION_MODE_OFFSET,
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- bp->e1hmf);
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+ bp->mf_mode);
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}
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/* Zero this manually as its initialization is
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@@ -4418,7 +4418,7 @@ static int bnx2x_init_hw_common(struct bnx2x *bp, u32 load_code)
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bnx2x_init_block(bp, MISC_BLOCK, COMMON_STAGE);
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if (CHIP_IS_E1H(bp))
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- REG_WR(bp, MISC_REG_E1HMF_MODE, IS_E1HMF(bp));
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+ REG_WR(bp, MISC_REG_E1HMF_MODE, IS_MF(bp));
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REG_WR(bp, MISC_REG_LCPLL_CTRL_REG_2, 0x100);
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msleep(30);
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@@ -4518,7 +4518,7 @@ static int bnx2x_init_hw_common(struct bnx2x *bp, u32 load_code)
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REG_WR(bp, PRS_REG_NIC_MODE, 1);
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#endif
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if (CHIP_IS_E1H(bp))
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- REG_WR(bp, PRS_REG_E1HOV_MODE, IS_E1HMF(bp));
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+ REG_WR(bp, PRS_REG_E1HOV_MODE, IS_MF(bp));
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bnx2x_init_block(bp, TSDM_BLOCK, COMMON_STAGE);
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bnx2x_init_block(bp, CSDM_BLOCK, COMMON_STAGE);
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@@ -4596,8 +4596,8 @@ static int bnx2x_init_hw_common(struct bnx2x *bp, u32 load_code)
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bnx2x_init_block(bp, NIG_BLOCK, COMMON_STAGE);
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if (CHIP_IS_E1H(bp)) {
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- REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_E1HMF(bp));
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- REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_E1HMF(bp));
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+ REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
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+ REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF(bp));
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}
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if (CHIP_REV_IS_SLOW(bp))
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@@ -4692,7 +4692,7 @@ static int bnx2x_init_hw_port(struct bnx2x *bp)
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low = 0;
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high = 513;
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} else {
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- if (IS_E1HMF(bp))
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+ if (IS_MF(bp))
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low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
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else if (bp->dev->mtu > 4096) {
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if (bp->flags & ONE_PORT_FLAG)
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@@ -4758,7 +4758,7 @@ static int bnx2x_init_hw_port(struct bnx2x *bp)
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* - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
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* bits 4-7 are used for "per vn group attention" */
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REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4,
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- (IS_E1HMF(bp) ? 0xF7 : 0x7));
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+ (IS_MF(bp) ? 0xF7 : 0x7));
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bnx2x_init_block(bp, PXPCS_BLOCK, init_stage);
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bnx2x_init_block(bp, EMAC0_BLOCK, init_stage);
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@@ -4771,9 +4771,9 @@ static int bnx2x_init_hw_port(struct bnx2x *bp)
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REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
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if (CHIP_IS_E1H(bp)) {
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- /* 0x2 disable e1hov, 0x1 enable */
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+ /* 0x2 disable mf_ov, 0x1 enable */
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REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
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- (IS_E1HMF(bp) ? 0x1 : 0x2));
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+ (IS_MF(bp) ? 0x1 : 0x2));
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{
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REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
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@@ -4883,9 +4883,9 @@ static int bnx2x_init_hw_func(struct bnx2x *bp)
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bnx2x_init_block(bp, CFC_BLOCK, FUNC0_STAGE + func);
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- if (IS_E1HMF(bp)) {
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+ if (IS_MF(bp)) {
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REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
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- REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->e1hov);
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+ REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
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}
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bnx2x_init_block(bp, MISC_AEU_BLOCK, FUNC0_STAGE + func);
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@@ -7189,8 +7189,8 @@ static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
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bp->igu_base_sb = 0;
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bp->igu_sb_cnt = min_t(u8, FP_SB_MAX_E1x, bp->l2_cid_count);
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- bp->e1hov = 0;
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- bp->e1hmf = 0;
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+ bp->mf_ov = 0;
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+ bp->mf_mode = 0;
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if (CHIP_IS_E1H(bp) && !BP_NOMCP(bp)) {
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bp->common.mf_cfg_base = bp->common.shmem_base +
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@@ -7202,19 +7202,19 @@ static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
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val = (MF_CFG_RD(bp, func_mf_config[FUNC_0].e1hov_tag) &
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FUNC_MF_CFG_E1HOV_TAG_MASK);
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if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
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- bp->e1hmf = 1;
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+ bp->mf_mode = 1;
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BNX2X_DEV_INFO("%s function mode\n",
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- IS_E1HMF(bp) ? "multi" : "single");
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+ IS_MF(bp) ? "multi" : "single");
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- if (IS_E1HMF(bp)) {
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+ if (IS_MF(bp)) {
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val = (MF_CFG_RD(bp, func_mf_config[func].
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e1hov_tag) &
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FUNC_MF_CFG_E1HOV_TAG_MASK);
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if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
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- bp->e1hov = val;
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+ bp->mf_ov = val;
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BNX2X_DEV_INFO("E1HOV for func %d is %d "
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"(0x%04x)\n",
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- func, bp->e1hov, bp->e1hov);
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+ func, bp->mf_ov, bp->mf_ov);
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} else {
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BNX2X_ERROR("No valid E1HOV for func %d,"
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" aborting\n", func);
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@@ -7230,7 +7230,7 @@ static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
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}
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/* adjust igu_sb_cnt to MF */
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- if (IS_E1HMF(bp))
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+ if (IS_MF(bp))
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bp->igu_sb_cnt /= E1HVN_MAX;
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if (!BP_NOMCP(bp)) {
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@@ -7241,7 +7241,7 @@ static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
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BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
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}
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- if (IS_E1HMF(bp)) {
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+ if (IS_MF(bp)) {
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val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
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val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
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if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
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