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@@ -461,7 +461,8 @@ int r300_gpu_reset(struct radeon_device *rdev)
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*/
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void r300_mc_init(struct radeon_device *rdev)
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{
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- uint32_t tmp;
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+ u64 base;
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+ u32 tmp;
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/* DDR for all card after R300 & IGP */
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rdev->mc.vram_is_ddr = true;
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@@ -474,6 +475,10 @@ void r300_mc_init(struct radeon_device *rdev)
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default: rdev->mc.vram_width = 128; break;
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}
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r100_vram_init_sizes(rdev);
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+ base = rdev->mc.aper_base;
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+ if (rdev->flags & RADEON_IS_IGP)
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+ base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
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+ radeon_vram_location(rdev, &rdev->mc, base);
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if (!(rdev->flags & RADEON_IS_AGP))
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radeon_gtt_location(rdev, &rdev->mc);
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}
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