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@@ -64,12 +64,21 @@
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/* Default value */
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#define IMX_I2C_BIT_RATE 100000 /* 100kHz */
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-/* IMX I2C registers */
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+/* IMX I2C registers:
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+ * the I2C register offset is different between SoCs,
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+ * to provid support for all these chips, split the
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+ * register offset into a fixed base address and a
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+ * variable shift value, then the full register offset
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+ * will be calculated by
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+ * reg_off = ( reg_base_addr << reg_shift)
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+ */
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#define IMX_I2C_IADR 0x00 /* i2c slave address */
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-#define IMX_I2C_IFDR 0x04 /* i2c frequency divider */
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-#define IMX_I2C_I2CR 0x08 /* i2c control */
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-#define IMX_I2C_I2SR 0x0C /* i2c status */
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-#define IMX_I2C_I2DR 0x10 /* i2c transfer data */
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+#define IMX_I2C_IFDR 0x01 /* i2c frequency divider */
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+#define IMX_I2C_I2CR 0x02 /* i2c control */
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+#define IMX_I2C_I2SR 0x03 /* i2c status */
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+#define IMX_I2C_I2DR 0x04 /* i2c transfer data */
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+
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+#define IMX_I2C_REGSHIFT 2
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/* Bits of IMX I2C registers */
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#define I2SR_RXAK 0x01
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@@ -163,13 +172,13 @@ static inline int is_imx1_i2c(struct imx_i2c_struct *i2c_imx)
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static inline void imx_i2c_write_reg(unsigned int val,
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struct imx_i2c_struct *i2c_imx, unsigned int reg)
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{
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- writeb(val, i2c_imx->base + reg);
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+ writeb(val, i2c_imx->base + (reg << IMX_I2C_REGSHIFT));
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}
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static inline unsigned char imx_i2c_read_reg(struct imx_i2c_struct *i2c_imx,
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unsigned int reg)
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{
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- return readb(i2c_imx->base + reg);
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+ return readb(i2c_imx->base + (reg << IMX_I2C_REGSHIFT));
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}
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/** Functions for IMX I2C adapter driver ***************************************
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