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@@ -4709,6 +4709,9 @@ static void rt2800_init_rfcsr_3390(struct rt2x00_dev *rt2x00dev)
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static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev)
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{
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+ u8 rfcsr;
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+ u32 reg;
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+
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rt2800_rf_init_calibration(rt2x00dev, 30);
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rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
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@@ -4742,6 +4745,20 @@ static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev)
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rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
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rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
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rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
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+
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+ rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
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+ rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
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+ rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
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+
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+ rt2800_register_read(rt2x00dev, LDO_CFG0, ®);
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+ rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3);
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+ rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1);
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+ rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
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+ msleep(1);
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+ rt2800_register_read(rt2x00dev, LDO_CFG0, ®);
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+ rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0);
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+ rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1);
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+ rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
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}
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static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev)
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@@ -4994,23 +5011,6 @@ static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
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return 0;
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}
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-
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- if (rt2x00_rt(rt2x00dev, RT3572)) {
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- rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
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- rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
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- rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
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-
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- rt2800_register_read(rt2x00dev, LDO_CFG0, ®);
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- rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3);
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- rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1);
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- rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
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- msleep(1);
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- rt2800_register_read(rt2x00dev, LDO_CFG0, ®);
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- rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0);
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- rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1);
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- rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
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- }
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-
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/*
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* Set RX Filter calibration for 20MHz and 40MHz
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*/
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