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@@ -1543,6 +1543,7 @@ static void iwl3945_rx_handle(struct iwl_priv *priv)
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"r = %d, i = %d, %s, 0x%02x\n", r, i,
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get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
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priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
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+ priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
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} else {
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/* No handling needed */
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IWL_DEBUG(priv, IWL_DL_HCMD | IWL_DL_RX | IWL_DL_ISR,
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@@ -1845,6 +1846,7 @@ static void iwl3945_irq_tasklet(struct iwl_priv *priv)
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/* Tell the device to stop sending interrupts */
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iwl_disable_interrupts(priv);
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+ priv->isr_stats.hw++;
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iwl_irq_handle_error(priv);
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handled |= CSR_INT_BIT_HW_ERR;
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@@ -1857,13 +1859,17 @@ static void iwl3945_irq_tasklet(struct iwl_priv *priv)
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#ifdef CONFIG_IWLWIFI_DEBUG
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if (priv->debug_level & (IWL_DL_ISR)) {
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/* NIC fires this, but we don't use it, redundant with WAKEUP */
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- if (inta & CSR_INT_BIT_SCD)
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+ if (inta & CSR_INT_BIT_SCD) {
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IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
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"the frame/frames.\n");
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+ priv->isr_stats.sch++;
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+ }
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/* Alive notification via Rx interrupt will do the real work */
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- if (inta & CSR_INT_BIT_ALIVE)
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+ if (inta & CSR_INT_BIT_ALIVE) {
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IWL_DEBUG_ISR(priv, "Alive interrupt\n");
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+ priv->isr_stats.alive++;
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+ }
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}
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#endif
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/* Safely ignore these bits for debug checks below */
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@@ -1873,6 +1879,8 @@ static void iwl3945_irq_tasklet(struct iwl_priv *priv)
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if (inta & CSR_INT_BIT_SW_ERR) {
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IWL_ERR(priv, "Microcode SW error detected. "
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"Restarting 0x%X.\n", inta);
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+ priv->isr_stats.sw++;
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+ priv->isr_stats.sw_err = inta;
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iwl_irq_handle_error(priv);
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handled |= CSR_INT_BIT_SW_ERR;
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}
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@@ -1888,6 +1896,7 @@ static void iwl3945_irq_tasklet(struct iwl_priv *priv)
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iwl_txq_update_write_ptr(priv, &priv->txq[4]);
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iwl_txq_update_write_ptr(priv, &priv->txq[5]);
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+ priv->isr_stats.wakeup++;
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handled |= CSR_INT_BIT_WAKEUP;
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}
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@@ -1896,11 +1905,13 @@ static void iwl3945_irq_tasklet(struct iwl_priv *priv)
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* notifications from uCode come through here*/
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if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
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iwl3945_rx_handle(priv);
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+ priv->isr_stats.rx++;
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handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
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}
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if (inta & CSR_INT_BIT_FH_TX) {
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IWL_DEBUG_ISR(priv, "Tx interrupt\n");
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+ priv->isr_stats.tx++;
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iwl_write32(priv, CSR_FH_INT_STATUS, (1 << 6));
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if (!iwl_grab_nic_access(priv)) {
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@@ -1911,8 +1922,10 @@ static void iwl3945_irq_tasklet(struct iwl_priv *priv)
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handled |= CSR_INT_BIT_FH_TX;
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}
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- if (inta & ~handled)
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+ if (inta & ~handled) {
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IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
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+ priv->isr_stats.unhandled++;
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+ }
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if (inta & ~CSR_INI_SET_MASK) {
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IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
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