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@@ -1276,6 +1276,17 @@ struct radeon_phase_shedding_limits_table {
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struct radeon_phase_shedding_limits_entry *entries;
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};
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+struct radeon_uvd_clock_voltage_dependency_entry {
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+ u32 vclk;
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+ u32 dclk;
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+ u16 v;
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+};
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+
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+struct radeon_uvd_clock_voltage_dependency_table {
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+ u8 count;
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+ struct radeon_uvd_clock_voltage_dependency_entry *entries;
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+};
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+
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struct radeon_ppm_table {
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u8 ppm_design;
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u16 cpu_core_number;
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@@ -1294,6 +1305,7 @@ struct radeon_dpm_dynamic_state {
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struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
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struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
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struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
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+ struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
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struct radeon_clock_array valid_sclk_values;
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struct radeon_clock_array valid_mclk_values;
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struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
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