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@@ -0,0 +1,870 @@
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+/* fuc microcode for copy engine on nva3- chipsets
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+ *
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+ * Copyright 2011 Red Hat Inc.
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+ *
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+ * Permission is hereby granted, free of charge, to any person obtaining a
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+ * copy of this software and associated documentation files (the "Software"),
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+ * to deal in the Software without restriction, including without limitation
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+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
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+ * and/or sell copies of the Software, and to permit persons to whom the
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+ * Software is furnished to do so, subject to the following conditions:
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+ *
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+ * The above copyright notice and this permission notice shall be included in
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+ * all copies or substantial portions of the Software.
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+ *
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+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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+ * OTHER DEALINGS IN THE SOFTWARE.
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+ *
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+ * Authors: Ben Skeggs
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+ */
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+
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+/* To build for nva3:nvc0
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+ * m4 -DNVA3 nva3_copy.fuc | envyas -a -w -m fuc -V nva3 -o nva3_copy.fuc.h
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+ *
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+ * To build for nvc0-
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+ * m4 -DNVC0 nva3_copy.fuc | envyas -a -w -m fuc -V nva3 -o nvc0_copy.fuc.h
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+ */
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+
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+ifdef(`NVA3',
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+.section nva3_pcopy_data,
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+.section nvc0_pcopy_data
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+)
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+
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+ctx_object: .b32 0
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+ifdef(`NVA3',
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+ctx_dma:
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+ctx_dma_query: .b32 0
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+ctx_dma_src: .b32 0
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+ctx_dma_dst: .b32 0
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+,)
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+.equ ctx_dma_count 3
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+ctx_query_address_high: .b32 0
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+ctx_query_address_low: .b32 0
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+ctx_query_counter: .b32 0
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+ctx_src_address_high: .b32 0
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+ctx_src_address_low: .b32 0
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+ctx_src_pitch: .b32 0
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+ctx_src_tile_mode: .b32 0
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+ctx_src_xsize: .b32 0
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+ctx_src_ysize: .b32 0
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+ctx_src_zsize: .b32 0
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+ctx_src_zoff: .b32 0
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+ctx_src_xoff: .b32 0
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+ctx_src_yoff: .b32 0
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+ctx_src_cpp: .b32 0
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+ctx_dst_address_high: .b32 0
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+ctx_dst_address_low: .b32 0
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+ctx_dst_pitch: .b32 0
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+ctx_dst_tile_mode: .b32 0
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+ctx_dst_xsize: .b32 0
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+ctx_dst_ysize: .b32 0
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+ctx_dst_zsize: .b32 0
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+ctx_dst_zoff: .b32 0
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+ctx_dst_xoff: .b32 0
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+ctx_dst_yoff: .b32 0
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+ctx_dst_cpp: .b32 0
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+ctx_format: .b32 0
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+ctx_swz_const0: .b32 0
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+ctx_swz_const1: .b32 0
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+ctx_xcnt: .b32 0
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+ctx_ycnt: .b32 0
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+.align 256
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+
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+dispatch_table:
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+// mthd 0x0000, NAME
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+.b16 0x000 1
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+.b32 ctx_object ~0xffffffff
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+// mthd 0x0100, NOP
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+.b16 0x040 1
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+.b32 0x00010000 + cmd_nop ~0xffffffff
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+// mthd 0x0140, PM_TRIGGER
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+.b16 0x050 1
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+.b32 0x00010000 + cmd_pm_trigger ~0xffffffff
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+ifdef(`NVA3', `
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+// mthd 0x0180-0x018c, DMA_
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+.b16 0x060 ctx_dma_count
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+dispatch_dma:
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+.b32 0x00010000 + cmd_dma ~0xffffffff
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+.b32 0x00010000 + cmd_dma ~0xffffffff
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+.b32 0x00010000 + cmd_dma ~0xffffffff
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+',)
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+// mthd 0x0200-0x0218, SRC_TILE
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+.b16 0x80 7
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+.b32 ctx_src_tile_mode ~0x00000fff
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+.b32 ctx_src_xsize ~0x0007ffff
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+.b32 ctx_src_ysize ~0x00001fff
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+.b32 ctx_src_zsize ~0x000007ff
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+.b32 ctx_src_zoff ~0x00000fff
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+.b32 ctx_src_xoff ~0x0007ffff
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+.b32 ctx_src_yoff ~0x00001fff
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+// mthd 0x0220-0x0238, DST_TILE
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+.b16 0x88 7
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+.b32 ctx_dst_tile_mode ~0x00000fff
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+.b32 ctx_dst_xsize ~0x0007ffff
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+.b32 ctx_dst_ysize ~0x00001fff
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+.b32 ctx_dst_zsize ~0x000007ff
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+.b32 ctx_dst_zoff ~0x00000fff
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+.b32 ctx_dst_xoff ~0x0007ffff
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+.b32 ctx_dst_yoff ~0x00001fff
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+// mthd 0x0300-0x0304, EXEC, WRCACHE_FLUSH
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+.b16 0xc0 2
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+.b32 0x00010000 + cmd_exec ~0xffffffff
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+.b32 0x00010000 + cmd_wrcache_flush ~0xffffffff
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+// mthd 0x030c-0x0340, various stuff
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+.b16 0xc3 14
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+.b32 ctx_src_address_high ~0x000000ff
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+.b32 ctx_src_address_low ~0xfffffff0
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+.b32 ctx_dst_address_high ~0x000000ff
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+.b32 ctx_dst_address_low ~0xfffffff0
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+.b32 ctx_src_pitch ~0x0007ffff
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+.b32 ctx_dst_pitch ~0x0007ffff
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+.b32 ctx_xcnt ~0x0000ffff
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+.b32 ctx_ycnt ~0x00001fff
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+.b32 ctx_format ~0x0333ffff
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+.b32 ctx_swz_const0 ~0xffffffff
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+.b32 ctx_swz_const1 ~0xffffffff
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+.b32 ctx_query_address_high ~0x000000ff
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+.b32 ctx_query_address_low ~0xffffffff
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+.b32 ctx_query_counter ~0xffffffff
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+.b16 0x800 0
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+
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+ifdef(`NVA3',
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+.section nva3_pcopy_code,
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+.section nvc0_pcopy_code
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+)
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+
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+main:
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+ clear b32 $r0
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+ mov $sp $r0
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+
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+ // setup i0 handler and route fifo and ctxswitch to it
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+ mov $r1 ih
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+ mov $iv0 $r1
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+ mov $r1 0x400
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+ movw $r2 0xfff3
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+ sethi $r2 0
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+ iowr I[$r2 + 0x300] $r2
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+
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+ // enable interrupts
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+ or $r2 0xc
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+ iowr I[$r1] $r2
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+ bset $flags ie0
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+
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+ // enable fifo access and context switching
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+ mov $r1 0x1200
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+ mov $r2 3
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+ iowr I[$r1] $r2
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+
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+ // sleep forever, waking for interrupts
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+ bset $flags $p0
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+ spin:
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+ sleep $p0
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+ bra spin
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+
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+// i0 handler
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+ih:
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+ iord $r1 I[$r0 + 0x200]
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+
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+ and $r2 $r1 0x00000008
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+ bra e ih_no_chsw
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+ call chsw
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+ ih_no_chsw:
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+ and $r2 $r1 0x00000004
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+ bra e ih_no_cmd
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+ call dispatch
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+
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+ ih_no_cmd:
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+ and $r1 $r1 0x0000000c
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+ iowr I[$r0 + 0x100] $r1
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+ iret
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+
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+// $p1 direction (0 = unload, 1 = load)
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+// $r3 channel
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+swctx:
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+ mov $r4 0x7700
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+ mov $xtargets $r4
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+ifdef(`NVA3', `
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+ // target 7 hardcoded to ctx dma object
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+ mov $xdbase $r0
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+', ` // NVC0
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+ // read SCRATCH3 to decide if we are PCOPY0 or PCOPY1
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+ mov $r4 0x2100
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+ iord $r4 I[$r4 + 0]
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+ and $r4 1
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+ shl b32 $r4 4
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+ add b32 $r4 0x30
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+
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+ // channel is in vram
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+ mov $r15 0x61c
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+ shl b32 $r15 6
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+ mov $r5 0x114
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+ iowrs I[$r15] $r5
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+
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+ // read 16-byte PCOPYn info, containing context pointer, from channel
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+ shl b32 $r5 $r3 4
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+ add b32 $r5 2
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+ mov $xdbase $r5
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+ mov $r5 $sp
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+ // get a chunk of stack space, aligned to 256 byte boundary
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+ sub b32 $r5 0x100
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+ mov $r6 0xff
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+ not b32 $r6
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+ and $r5 $r6
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+ sethi $r5 0x00020000
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+ xdld $r4 $r5
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+ xdwait
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+ sethi $r5 0
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+
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+ // set context pointer, from within channel VM
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+ mov $r14 0
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+ iowrs I[$r15] $r14
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+ ld b32 $r4 D[$r5 + 0]
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+ shr b32 $r4 8
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+ ld b32 $r6 D[$r5 + 4]
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+ shl b32 $r6 24
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+ or $r4 $r6
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+ mov $xdbase $r4
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+')
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+ // 256-byte context, at start of data segment
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+ mov b32 $r4 $r0
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+ sethi $r4 0x60000
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+
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+ // swap!
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+ bra $p1 swctx_load
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+ xdst $r0 $r4
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+ bra swctx_done
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+ swctx_load:
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+ xdld $r0 $r4
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+ swctx_done:
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+ xdwait
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+ ret
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+
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+chsw:
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+ // read current channel
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+ mov $r2 0x1400
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+ iord $r3 I[$r2]
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+
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+ // if it's active, unload it and return
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+ xbit $r15 $r3 0x1e
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+ bra e chsw_no_unload
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+ bclr $flags $p1
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+ call swctx
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+ bclr $r3 0x1e
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+ iowr I[$r2] $r3
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+ mov $r4 1
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+ iowr I[$r2 + 0x200] $r4
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+ ret
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+
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+ // read next channel
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+ chsw_no_unload:
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+ iord $r3 I[$r2 + 0x100]
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+
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+ // is there a channel waiting to be loaded?
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+ xbit $r13 $r3 0x1e
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+ bra e chsw_finish_load
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+ bset $flags $p1
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+ call swctx
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+ifdef(`NVA3',
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+ // load dma objects back into TARGET regs
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+ mov $r5 ctx_dma
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+ mov $r6 ctx_dma_count
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+ chsw_load_ctx_dma:
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+ ld b32 $r7 D[$r5 + $r6 * 4]
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+ add b32 $r8 $r6 0x180
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+ shl b32 $r8 8
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+ iowr I[$r8] $r7
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+ sub b32 $r6 1
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+ bra nc chsw_load_ctx_dma
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+,)
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+
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+ chsw_finish_load:
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+ mov $r3 2
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+ iowr I[$r2 + 0x200] $r3
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+ ret
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+
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+dispatch:
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+ // read incoming fifo command
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+ mov $r3 0x1900
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+ iord $r2 I[$r3 + 0x100]
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+ iord $r3 I[$r3 + 0x000]
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+ and $r4 $r2 0x7ff
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+ // $r2 will be used to store exception data
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+ shl b32 $r2 0x10
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+
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+ // lookup method in the dispatch table, ILLEGAL_MTHD if not found
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+ mov $r5 dispatch_table
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+ clear b32 $r6
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+ clear b32 $r7
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+ dispatch_loop:
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+ ld b16 $r6 D[$r5 + 0]
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+ ld b16 $r7 D[$r5 + 2]
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+ add b32 $r5 4
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+ cmpu b32 $r4 $r6
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+ bra c dispatch_illegal_mthd
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+ add b32 $r7 $r6
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+ cmpu b32 $r4 $r7
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+ bra c dispatch_valid_mthd
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+ sub b32 $r7 $r6
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+ shl b32 $r7 3
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+ add b32 $r5 $r7
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+ bra dispatch_loop
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+
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+ // ensure no bits set in reserved fields, INVALID_BITFIELD
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+ dispatch_valid_mthd:
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+ sub b32 $r4 $r6
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+ shl b32 $r4 3
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+ add b32 $r4 $r5
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+ ld b32 $r5 D[$r4 + 4]
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+ and $r5 $r3
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+ cmpu b32 $r5 0
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+ bra ne dispatch_invalid_bitfield
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+
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+ // depending on dispatch flags: execute method, or save data as state
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+ ld b16 $r5 D[$r4 + 0]
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+ ld b16 $r6 D[$r4 + 2]
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+ cmpu b32 $r6 0
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+ bra ne dispatch_cmd
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+ st b32 D[$r5] $r3
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+ bra dispatch_done
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+ dispatch_cmd:
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+ bclr $flags $p1
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+ call $r5
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+ bra $p1 dispatch_error
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+ bra dispatch_done
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+
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+ dispatch_invalid_bitfield:
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+ or $r2 2
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+ dispatch_illegal_mthd:
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+ or $r2 1
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+
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+ // store exception data in SCRATCH0/SCRATCH1, signal hostirq
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+ dispatch_error:
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+ mov $r4 0x1000
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+ iowr I[$r4 + 0x000] $r2
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+ iowr I[$r4 + 0x100] $r3
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+ mov $r2 0x40
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+ iowr I[$r0] $r2
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+ hostirq_wait:
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+ iord $r2 I[$r0 + 0x200]
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+ and $r2 0x40
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+ cmpu b32 $r2 0
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+ bra ne hostirq_wait
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+
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+ dispatch_done:
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+ mov $r2 0x1d00
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+ mov $r3 1
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+ iowr I[$r2] $r3
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+ ret
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+
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+// No-operation
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+//
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+// Inputs:
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+// $r1: irqh state
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+// $r2: hostirq state
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+// $r3: data
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+// $r4: dispatch table entry
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+// Outputs:
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+// $r1: irqh state
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+// $p1: set on error
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+// $r2: hostirq state
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+// $r3: data
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+cmd_nop:
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+ ret
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+
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+// PM_TRIGGER
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+//
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+// Inputs:
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+// $r1: irqh state
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+// $r2: hostirq state
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+// $r3: data
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+// $r4: dispatch table entry
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+// Outputs:
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+// $r1: irqh state
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+// $p1: set on error
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+// $r2: hostirq state
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+// $r3: data
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+cmd_pm_trigger:
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+ mov $r2 0x2200
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+ clear b32 $r3
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+ sethi $r3 0x20000
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+ iowr I[$r2] $r3
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+ ret
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+
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+ifdef(`NVA3',
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+// SET_DMA_* method handler
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+//
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+// Inputs:
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+// $r1: irqh state
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+// $r2: hostirq state
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+// $r3: data
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|
|
+// $r4: dispatch table entry
|
|
|
+// Outputs:
|
|
|
+// $r1: irqh state
|
|
|
+// $p1: set on error
|
|
|
+// $r2: hostirq state
|
|
|
+// $r3: data
|
|
|
+cmd_dma:
|
|
|
+ sub b32 $r4 dispatch_dma
|
|
|
+ shr b32 $r4 1
|
|
|
+ bset $r3 0x1e
|
|
|
+ st b32 D[$r4 + ctx_dma] $r3
|
|
|
+ add b32 $r4 0x600
|
|
|
+ shl b32 $r4 6
|
|
|
+ iowr I[$r4] $r3
|
|
|
+ ret
|
|
|
+,)
|
|
|
+
|
|
|
+// Calculates the hw swizzle mask and adjusts the surface's xcnt to match
|
|
|
+//
|
|
|
+cmd_exec_set_format:
|
|
|
+ // zero out a chunk of the stack to store the swizzle into
|
|
|
+ add $sp -0x10
|
|
|
+ st b32 D[$sp + 0x00] $r0
|
|
|
+ st b32 D[$sp + 0x04] $r0
|
|
|
+ st b32 D[$sp + 0x08] $r0
|
|
|
+ st b32 D[$sp + 0x0c] $r0
|
|
|
+
|
|
|
+ // extract cpp, src_ncomp and dst_ncomp from FORMAT
|
|
|
+ ld b32 $r4 D[$r0 + ctx_format]
|
|
|
+ extr $r5 $r4 16:17
|
|
|
+ add b32 $r5 1
|
|
|
+ extr $r6 $r4 20:21
|
|
|
+ add b32 $r6 1
|
|
|
+ extr $r7 $r4 24:25
|
|
|
+ add b32 $r7 1
|
|
|
+
|
|
|
+ // convert FORMAT swizzle mask to hw swizzle mask
|
|
|
+ bclr $flags $p2
|
|
|
+ clear b32 $r8
|
|
|
+ clear b32 $r9
|
|
|
+ ncomp_loop:
|
|
|
+ and $r10 $r4 0xf
|
|
|
+ shr b32 $r4 4
|
|
|
+ clear b32 $r11
|
|
|
+ bpc_loop:
|
|
|
+ cmpu b8 $r10 4
|
|
|
+ bra nc cmp_c0
|
|
|
+ mulu $r12 $r10 $r5
|
|
|
+ add b32 $r12 $r11
|
|
|
+ bset $flags $p2
|
|
|
+ bra bpc_next
|
|
|
+ cmp_c0:
|
|
|
+ bra ne cmp_c1
|
|
|
+ mov $r12 0x10
|
|
|
+ add b32 $r12 $r11
|
|
|
+ bra bpc_next
|
|
|
+ cmp_c1:
|
|
|
+ cmpu b8 $r10 6
|
|
|
+ bra nc cmp_zero
|
|
|
+ mov $r12 0x14
|
|
|
+ add b32 $r12 $r11
|
|
|
+ bra bpc_next
|
|
|
+ cmp_zero:
|
|
|
+ mov $r12 0x80
|
|
|
+ bpc_next:
|
|
|
+ st b8 D[$sp + $r8] $r12
|
|
|
+ add b32 $r8 1
|
|
|
+ add b32 $r11 1
|
|
|
+ cmpu b32 $r11 $r5
|
|
|
+ bra c bpc_loop
|
|
|
+ add b32 $r9 1
|
|
|
+ cmpu b32 $r9 $r7
|
|
|
+ bra c ncomp_loop
|
|
|
+
|
|
|
+ // SRC_XCNT = (xcnt * src_cpp), or 0 if no src ref in swz (hw will hang)
|
|
|
+ mulu $r6 $r5
|
|
|
+ st b32 D[$r0 + ctx_src_cpp] $r6
|
|
|
+ ld b32 $r8 D[$r0 + ctx_xcnt]
|
|
|
+ mulu $r6 $r8
|
|
|
+ bra $p2 dst_xcnt
|
|
|
+ clear b32 $r6
|
|
|
+
|
|
|
+ dst_xcnt:
|
|
|
+ mulu $r7 $r5
|
|
|
+ st b32 D[$r0 + ctx_dst_cpp] $r7
|
|
|
+ mulu $r7 $r8
|
|
|
+
|
|
|
+ mov $r5 0x810
|
|
|
+ shl b32 $r5 6
|
|
|
+ iowr I[$r5 + 0x000] $r6
|
|
|
+ iowr I[$r5 + 0x100] $r7
|
|
|
+ add b32 $r5 0x800
|
|
|
+ ld b32 $r6 D[$r0 + ctx_dst_cpp]
|
|
|
+ sub b32 $r6 1
|
|
|
+ shl b32 $r6 8
|
|
|
+ ld b32 $r7 D[$r0 + ctx_src_cpp]
|
|
|
+ sub b32 $r7 1
|
|
|
+ or $r6 $r7
|
|
|
+ iowr I[$r5 + 0x000] $r6
|
|
|
+ add b32 $r5 0x100
|
|
|
+ ld b32 $r6 D[$sp + 0x00]
|
|
|
+ iowr I[$r5 + 0x000] $r6
|
|
|
+ ld b32 $r6 D[$sp + 0x04]
|
|
|
+ iowr I[$r5 + 0x100] $r6
|
|
|
+ ld b32 $r6 D[$sp + 0x08]
|
|
|
+ iowr I[$r5 + 0x200] $r6
|
|
|
+ ld b32 $r6 D[$sp + 0x0c]
|
|
|
+ iowr I[$r5 + 0x300] $r6
|
|
|
+ add b32 $r5 0x400
|
|
|
+ ld b32 $r6 D[$r0 + ctx_swz_const0]
|
|
|
+ iowr I[$r5 + 0x000] $r6
|
|
|
+ ld b32 $r6 D[$r0 + ctx_swz_const1]
|
|
|
+ iowr I[$r5 + 0x100] $r6
|
|
|
+ add $sp 0x10
|
|
|
+ ret
|
|
|
+
|
|
|
+// Setup to handle a tiled surface
|
|
|
+//
|
|
|
+// Calculates a number of parameters the hardware requires in order
|
|
|
+// to correctly handle tiling.
|
|
|
+//
|
|
|
+// Offset calculation is performed as follows (Tp/Th/Td from TILE_MODE):
|
|
|
+// nTx = round_up(w * cpp, 1 << Tp) >> Tp
|
|
|
+// nTy = round_up(h, 1 << Th) >> Th
|
|
|
+// Txo = (x * cpp) & ((1 << Tp) - 1)
|
|
|
+// Tx = (x * cpp) >> Tp
|
|
|
+// Tyo = y & ((1 << Th) - 1)
|
|
|
+// Ty = y >> Th
|
|
|
+// Tzo = z & ((1 << Td) - 1)
|
|
|
+// Tz = z >> Td
|
|
|
+//
|
|
|
+// off = (Tzo << Tp << Th) + (Tyo << Tp) + Txo
|
|
|
+// off += ((Tz * nTy * nTx)) + (Ty * nTx) + Tx) << Td << Th << Tp;
|
|
|
+//
|
|
|
+// Inputs:
|
|
|
+// $r4: hw command (0x104800)
|
|
|
+// $r5: ctx offset adjustment for src/dst selection
|
|
|
+// $p2: set if dst surface
|
|
|
+//
|
|
|
+cmd_exec_set_surface_tiled:
|
|
|
+ // translate TILE_MODE into Tp, Th, Td shift values
|
|
|
+ ld b32 $r7 D[$r5 + ctx_src_tile_mode]
|
|
|
+ extr $r9 $r7 8:11
|
|
|
+ extr $r8 $r7 4:7
|
|
|
+ifdef(`NVA3',
|
|
|
+ add b32 $r8 2
|
|
|
+,
|
|
|
+ add b32 $r8 3
|
|
|
+)
|
|
|
+ extr $r7 $r7 0:3
|
|
|
+ cmp b32 $r7 0xe
|
|
|
+ bra ne xtile64
|
|
|
+ mov $r7 4
|
|
|
+ bra xtileok
|
|
|
+ xtile64:
|
|
|
+ xbit $r7 $flags $p2
|
|
|
+ add b32 $r7 17
|
|
|
+ bset $r4 $r7
|
|
|
+ mov $r7 6
|
|
|
+ xtileok:
|
|
|
+
|
|
|
+ // Op = (x * cpp) & ((1 << Tp) - 1)
|
|
|
+ // Tx = (x * cpp) >> Tp
|
|
|
+ ld b32 $r10 D[$r5 + ctx_src_xoff]
|
|
|
+ ld b32 $r11 D[$r5 + ctx_src_cpp]
|
|
|
+ mulu $r10 $r11
|
|
|
+ mov $r11 1
|
|
|
+ shl b32 $r11 $r7
|
|
|
+ sub b32 $r11 1
|
|
|
+ and $r12 $r10 $r11
|
|
|
+ shr b32 $r10 $r7
|
|
|
+
|
|
|
+ // Tyo = y & ((1 << Th) - 1)
|
|
|
+ // Ty = y >> Th
|
|
|
+ ld b32 $r13 D[$r5 + ctx_src_yoff]
|
|
|
+ mov $r14 1
|
|
|
+ shl b32 $r14 $r8
|
|
|
+ sub b32 $r14 1
|
|
|
+ and $r11 $r13 $r14
|
|
|
+ shr b32 $r13 $r8
|
|
|
+
|
|
|
+ // YTILE = ((1 << Th) << 12) | ((1 << Th) - Tyo)
|
|
|
+ add b32 $r14 1
|
|
|
+ shl b32 $r15 $r14 12
|
|
|
+ sub b32 $r14 $r11
|
|
|
+ or $r15 $r14
|
|
|
+ xbit $r6 $flags $p2
|
|
|
+ add b32 $r6 0x208
|
|
|
+ shl b32 $r6 8
|
|
|
+ iowr I[$r6 + 0x000] $r15
|
|
|
+
|
|
|
+ // Op += Tyo << Tp
|
|
|
+ shl b32 $r11 $r7
|
|
|
+ add b32 $r12 $r11
|
|
|
+
|
|
|
+ // nTx = ((w * cpp) + ((1 << Tp) - 1) >> Tp)
|
|
|
+ ld b32 $r15 D[$r5 + ctx_src_xsize]
|
|
|
+ ld b32 $r11 D[$r5 + ctx_src_cpp]
|
|
|
+ mulu $r15 $r11
|
|
|
+ mov $r11 1
|
|
|
+ shl b32 $r11 $r7
|
|
|
+ sub b32 $r11 1
|
|
|
+ add b32 $r15 $r11
|
|
|
+ shr b32 $r15 $r7
|
|
|
+ push $r15
|
|
|
+
|
|
|
+ // nTy = (h + ((1 << Th) - 1)) >> Th
|
|
|
+ ld b32 $r15 D[$r5 + ctx_src_ysize]
|
|
|
+ mov $r11 1
|
|
|
+ shl b32 $r11 $r8
|
|
|
+ sub b32 $r11 1
|
|
|
+ add b32 $r15 $r11
|
|
|
+ shr b32 $r15 $r8
|
|
|
+ push $r15
|
|
|
+
|
|
|
+ // Tys = Tp + Th
|
|
|
+ // CFG_YZ_TILE_SIZE = ((1 << Th) >> 2) << Td
|
|
|
+ add b32 $r7 $r8
|
|
|
+ sub b32 $r8 2
|
|
|
+ mov $r11 1
|
|
|
+ shl b32 $r11 $r8
|
|
|
+ shl b32 $r11 $r9
|
|
|
+
|
|
|
+ // Tzo = z & ((1 << Td) - 1)
|
|
|
+ // Tz = z >> Td
|
|
|
+ // Op += Tzo << Tys
|
|
|
+ // Ts = Tys + Td
|
|
|
+ ld b32 $r8 D[$r5 + ctx_src_zoff]
|
|
|
+ mov $r14 1
|
|
|
+ shl b32 $r14 $r9
|
|
|
+ sub b32 $r14 1
|
|
|
+ and $r15 $r8 $r14
|
|
|
+ shl b32 $r15 $r7
|
|
|
+ add b32 $r12 $r15
|
|
|
+ add b32 $r7 $r9
|
|
|
+ shr b32 $r8 $r9
|
|
|
+
|
|
|
+ // Ot = ((Tz * nTy * nTx) + (Ty * nTx) + Tx) << Ts
|
|
|
+ pop $r15
|
|
|
+ pop $r9
|
|
|
+ mulu $r13 $r9
|
|
|
+ add b32 $r10 $r13
|
|
|
+ mulu $r8 $r9
|
|
|
+ mulu $r8 $r15
|
|
|
+ add b32 $r10 $r8
|
|
|
+ shl b32 $r10 $r7
|
|
|
+
|
|
|
+ // PITCH = (nTx - 1) << Ts
|
|
|
+ sub b32 $r9 1
|
|
|
+ shl b32 $r9 $r7
|
|
|
+ iowr I[$r6 + 0x200] $r9
|
|
|
+
|
|
|
+ // SRC_ADDRESS_LOW = (Ot + Op) & 0xffffffff
|
|
|
+ // CFG_ADDRESS_HIGH |= ((Ot + Op) >> 32) << 16
|
|
|
+ ld b32 $r7 D[$r5 + ctx_src_address_low]
|
|
|
+ ld b32 $r8 D[$r5 + ctx_src_address_high]
|
|
|
+ add b32 $r10 $r12
|
|
|
+ add b32 $r7 $r10
|
|
|
+ adc b32 $r8 0
|
|
|
+ shl b32 $r8 16
|
|
|
+ or $r8 $r11
|
|
|
+ sub b32 $r6 0x600
|
|
|
+ iowr I[$r6 + 0x000] $r7
|
|
|
+ add b32 $r6 0x400
|
|
|
+ iowr I[$r6 + 0x000] $r8
|
|
|
+ ret
|
|
|
+
|
|
|
+// Setup to handle a linear surface
|
|
|
+//
|
|
|
+// Nothing to see here.. Sets ADDRESS and PITCH, pretty non-exciting
|
|
|
+//
|
|
|
+cmd_exec_set_surface_linear:
|
|
|
+ xbit $r6 $flags $p2
|
|
|
+ add b32 $r6 0x202
|
|
|
+ shl b32 $r6 8
|
|
|
+ ld b32 $r7 D[$r5 + ctx_src_address_low]
|
|
|
+ iowr I[$r6 + 0x000] $r7
|
|
|
+ add b32 $r6 0x400
|
|
|
+ ld b32 $r7 D[$r5 + ctx_src_address_high]
|
|
|
+ shl b32 $r7 16
|
|
|
+ iowr I[$r6 + 0x000] $r7
|
|
|
+ add b32 $r6 0x400
|
|
|
+ ld b32 $r7 D[$r5 + ctx_src_pitch]
|
|
|
+ iowr I[$r6 + 0x000] $r7
|
|
|
+ ret
|
|
|
+
|
|
|
+// wait for regs to be available for use
|
|
|
+cmd_exec_wait:
|
|
|
+ push $r0
|
|
|
+ push $r1
|
|
|
+ mov $r0 0x800
|
|
|
+ shl b32 $r0 6
|
|
|
+ loop:
|
|
|
+ iord $r1 I[$r0]
|
|
|
+ and $r1 1
|
|
|
+ bra ne loop
|
|
|
+ pop $r1
|
|
|
+ pop $r0
|
|
|
+ ret
|
|
|
+
|
|
|
+cmd_exec_query:
|
|
|
+ // if QUERY_SHORT not set, write out { -, 0, TIME_LO, TIME_HI }
|
|
|
+ xbit $r4 $r3 13
|
|
|
+ bra ne query_counter
|
|
|
+ call cmd_exec_wait
|
|
|
+ mov $r4 0x80c
|
|
|
+ shl b32 $r4 6
|
|
|
+ ld b32 $r5 D[$r0 + ctx_query_address_low]
|
|
|
+ add b32 $r5 4
|
|
|
+ iowr I[$r4 + 0x000] $r5
|
|
|
+ iowr I[$r4 + 0x100] $r0
|
|
|
+ mov $r5 0xc
|
|
|
+ iowr I[$r4 + 0x200] $r5
|
|
|
+ add b32 $r4 0x400
|
|
|
+ ld b32 $r5 D[$r0 + ctx_query_address_high]
|
|
|
+ shl b32 $r5 16
|
|
|
+ iowr I[$r4 + 0x000] $r5
|
|
|
+ add b32 $r4 0x500
|
|
|
+ mov $r5 0x00000b00
|
|
|
+ sethi $r5 0x00010000
|
|
|
+ iowr I[$r4 + 0x000] $r5
|
|
|
+ mov $r5 0x00004040
|
|
|
+ shl b32 $r5 1
|
|
|
+ sethi $r5 0x80800000
|
|
|
+ iowr I[$r4 + 0x100] $r5
|
|
|
+ mov $r5 0x00001110
|
|
|
+ sethi $r5 0x13120000
|
|
|
+ iowr I[$r4 + 0x200] $r5
|
|
|
+ mov $r5 0x00001514
|
|
|
+ sethi $r5 0x17160000
|
|
|
+ iowr I[$r4 + 0x300] $r5
|
|
|
+ mov $r5 0x00002601
|
|
|
+ sethi $r5 0x00010000
|
|
|
+ mov $r4 0x800
|
|
|
+ shl b32 $r4 6
|
|
|
+ iowr I[$r4 + 0x000] $r5
|
|
|
+
|
|
|
+ // write COUNTER
|
|
|
+ query_counter:
|
|
|
+ call cmd_exec_wait
|
|
|
+ mov $r4 0x80c
|
|
|
+ shl b32 $r4 6
|
|
|
+ ld b32 $r5 D[$r0 + ctx_query_address_low]
|
|
|
+ iowr I[$r4 + 0x000] $r5
|
|
|
+ iowr I[$r4 + 0x100] $r0
|
|
|
+ mov $r5 0x4
|
|
|
+ iowr I[$r4 + 0x200] $r5
|
|
|
+ add b32 $r4 0x400
|
|
|
+ ld b32 $r5 D[$r0 + ctx_query_address_high]
|
|
|
+ shl b32 $r5 16
|
|
|
+ iowr I[$r4 + 0x000] $r5
|
|
|
+ add b32 $r4 0x500
|
|
|
+ mov $r5 0x00000300
|
|
|
+ iowr I[$r4 + 0x000] $r5
|
|
|
+ mov $r5 0x00001110
|
|
|
+ sethi $r5 0x13120000
|
|
|
+ iowr I[$r4 + 0x100] $r5
|
|
|
+ ld b32 $r5 D[$r0 + ctx_query_counter]
|
|
|
+ add b32 $r4 0x500
|
|
|
+ iowr I[$r4 + 0x000] $r5
|
|
|
+ mov $r5 0x00002601
|
|
|
+ sethi $r5 0x00010000
|
|
|
+ mov $r4 0x800
|
|
|
+ shl b32 $r4 6
|
|
|
+ iowr I[$r4 + 0x000] $r5
|
|
|
+ ret
|
|
|
+
|
|
|
+// Execute a copy operation
|
|
|
+//
|
|
|
+// Inputs:
|
|
|
+// $r1: irqh state
|
|
|
+// $r2: hostirq state
|
|
|
+// $r3: data
|
|
|
+// 000002000 QUERY_SHORT
|
|
|
+// 000001000 QUERY
|
|
|
+// 000000100 DST_LINEAR
|
|
|
+// 000000010 SRC_LINEAR
|
|
|
+// 000000001 FORMAT
|
|
|
+// $r4: dispatch table entry
|
|
|
+// Outputs:
|
|
|
+// $r1: irqh state
|
|
|
+// $p1: set on error
|
|
|
+// $r2: hostirq state
|
|
|
+// $r3: data
|
|
|
+cmd_exec:
|
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+ call cmd_exec_wait
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+
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+ // if format requested, call function to calculate it, otherwise
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+ // fill in cpp/xcnt for both surfaces as if (cpp == 1)
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+ xbit $r15 $r3 0
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+ bra e cmd_exec_no_format
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+ call cmd_exec_set_format
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+ mov $r4 0x200
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+ bra cmd_exec_init_src_surface
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+ cmd_exec_no_format:
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+ mov $r6 0x810
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+ shl b32 $r6 6
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+ mov $r7 1
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+ st b32 D[$r0 + ctx_src_cpp] $r7
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+ st b32 D[$r0 + ctx_dst_cpp] $r7
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+ ld b32 $r7 D[$r0 + ctx_xcnt]
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+ iowr I[$r6 + 0x000] $r7
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+ iowr I[$r6 + 0x100] $r7
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+ clear b32 $r4
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+
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+ cmd_exec_init_src_surface:
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+ bclr $flags $p2
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+ clear b32 $r5
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+ xbit $r15 $r3 4
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+ bra e src_tiled
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+ call cmd_exec_set_surface_linear
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+ bra cmd_exec_init_dst_surface
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+ src_tiled:
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+ call cmd_exec_set_surface_tiled
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+ bset $r4 7
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+
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+ cmd_exec_init_dst_surface:
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+ bset $flags $p2
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+ mov $r5 ctx_dst_address_high - ctx_src_address_high
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+ xbit $r15 $r3 8
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+ bra e dst_tiled
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+ call cmd_exec_set_surface_linear
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+ bra cmd_exec_kick
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+ dst_tiled:
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+ call cmd_exec_set_surface_tiled
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+ bset $r4 8
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+
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+ cmd_exec_kick:
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+ mov $r5 0x800
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+ shl b32 $r5 6
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+ ld b32 $r6 D[$r0 + ctx_ycnt]
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+ iowr I[$r5 + 0x100] $r6
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+ mov $r6 0x0041
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+ // SRC_TARGET = 1, DST_TARGET = 2
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+ sethi $r6 0x44000000
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+ or $r4 $r6
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+ iowr I[$r5] $r4
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+
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+ // if requested, queue up a QUERY write after the copy has completed
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+ xbit $r15 $r3 12
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+ bra e cmd_exec_done
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+ call cmd_exec_query
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+
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+ cmd_exec_done:
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+ ret
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+
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+// Flush write cache
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+//
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+// Inputs:
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+// $r1: irqh state
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+// $r2: hostirq state
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+// $r3: data
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+// $r4: dispatch table entry
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+// Outputs:
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+// $r1: irqh state
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+// $p1: set on error
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+// $r2: hostirq state
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+// $r3: data
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+cmd_wrcache_flush:
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+ mov $r2 0x2200
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+ clear b32 $r3
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+ sethi $r3 0x10000
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|
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+ iowr I[$r2] $r3
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+ ret
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+
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+.align 0x100
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Ben Skeggs