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@@ -2149,7 +2149,7 @@ qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
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scsi_qla_host_t *base_vha = NULL;
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struct qla_hw_data *ha;
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char pci_info[30];
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- char fw_str[30];
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+ char fw_str[30], wq_name[30];
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struct scsi_host_template *sht;
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int bars, mem_only = 0;
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uint16_t req_length = 0, rsp_length = 0;
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@@ -2319,6 +2319,7 @@ qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
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ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
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ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
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} else if (IS_QLA83XX(ha)) {
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+ ha->portnum = PCI_FUNC(ha->pdev->devfn);
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ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
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ha->mbx_count = MAILBOX_REGISTER_COUNT;
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req_length = REQUEST_ENTRY_CNT_24XX;
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@@ -2403,6 +2404,20 @@ qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
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base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
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base_vha->vp_idx;
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+ if (IS_QLA8031(ha)) {
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+ sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
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+ ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
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+ INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
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+
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+ sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
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+ ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
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+ INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
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+ INIT_WORK(&ha->idc_state_handler,
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+ qla83xx_idc_state_handler_work);
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+ INIT_WORK(&ha->nic_core_unrecoverable,
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+ qla83xx_nic_core_unrecoverable_work);
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+ }
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+
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/* Set the SG table size based on ISP type */
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if (!IS_FWI2_CAPABLE(ha)) {
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if (IS_QLA2100(ha))
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@@ -2500,7 +2515,7 @@ que_init:
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if (IS_QLA82XX(ha)) {
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qla82xx_idc_lock(ha);
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qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
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- QLA82XX_DEV_FAILED);
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+ QLA8XXX_DEV_FAILED);
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qla82xx_idc_unlock(ha);
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ql_log(ql_log_fatal, base_vha, 0x00d7,
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"HW State: FAILED.\n");
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@@ -2751,6 +2766,14 @@ qla2x00_remove_one(struct pci_dev *pdev)
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}
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mutex_unlock(&ha->vport_lock);
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+ if (IS_QLA8031(ha)) {
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+ ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
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+ "Clearing fcoe driver presence.\n");
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+ if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
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+ ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
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+ "Error while clearing DRV-Presence.\n");
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+ }
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+
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set_bit(UNLOADING, &base_vha->dpc_flags);
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qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
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@@ -2772,6 +2795,21 @@ qla2x00_remove_one(struct pci_dev *pdev)
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ha->wq = NULL;
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}
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+ /* Cancel all work and destroy DPC workqueues */
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+ if (ha->dpc_lp_wq) {
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+ cancel_work_sync(&ha->idc_aen);
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+ destroy_workqueue(ha->dpc_lp_wq);
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+ ha->dpc_lp_wq = NULL;
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+ }
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+
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+ if (ha->dpc_hp_wq) {
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+ cancel_work_sync(&ha->nic_core_reset);
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+ cancel_work_sync(&ha->idc_state_handler);
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+ cancel_work_sync(&ha->nic_core_unrecoverable);
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+ destroy_workqueue(ha->dpc_hp_wq);
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+ ha->dpc_hp_wq = NULL;
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+ }
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+
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/* Kill the kernel thread for this host */
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if (ha->dpc_thread) {
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struct task_struct *t = ha->dpc_thread;
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@@ -2838,7 +2876,6 @@ qla2x00_free_device(scsi_qla_host_t *vha)
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qla2x00_stop_dpc_thread(vha);
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qla25xx_delete_queues(vha);
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-
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if (ha->flags.fce_enabled)
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qla2x00_disable_fce_trace(vha, NULL, NULL);
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@@ -3709,6 +3746,637 @@ void qla2x00_relogin(struct scsi_qla_host *vha)
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}
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}
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+/* Schedule work on any of the dpc-workqueues */
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+void
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+qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
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+{
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+ struct qla_hw_data *ha = base_vha->hw;
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+
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+ switch (work_code) {
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+ case MBA_IDC_AEN: /* 0x8200 */
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+ if (ha->dpc_lp_wq)
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+ queue_work(ha->dpc_lp_wq, &ha->idc_aen);
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+ break;
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+
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+ case QLA83XX_NIC_CORE_RESET: /* 0x1 */
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+ if (!ha->flags.nic_core_reset_hdlr_active) {
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+ if (ha->dpc_hp_wq)
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+ queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
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+ } else
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+ ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
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+ "NIC Core reset is already active. Skip "
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+ "scheduling it again.\n");
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+ break;
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+ case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
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+ if (ha->dpc_hp_wq)
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+ queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
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+ break;
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+ case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
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+ if (ha->dpc_hp_wq)
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+ queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
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+ break;
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+ default:
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+ ql_log(ql_log_warn, base_vha, 0xb05f,
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+ "Unknow work-code=0x%x.\n", work_code);
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+ }
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+
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+ return;
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+}
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+
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+/* Work: Perform NIC Core Unrecoverable state handling */
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+void
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+qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
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+{
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+ struct qla_hw_data *ha =
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+ container_of(work, struct qla_hw_data, nic_core_reset);
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+ scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
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+ uint32_t dev_state = 0;
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+
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+ qla83xx_idc_lock(base_vha, 0);
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+ qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
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+ qla83xx_reset_ownership(base_vha);
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+ if (ha->flags.nic_core_reset_owner) {
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+ ha->flags.nic_core_reset_owner = 0;
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+ qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
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+ QLA8XXX_DEV_FAILED);
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+ ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
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+ qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
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+ }
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+ qla83xx_idc_unlock(base_vha, 0);
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+}
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+
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+/* Work: Execute IDC state handler */
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+void
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+qla83xx_idc_state_handler_work(struct work_struct *work)
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+{
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+ struct qla_hw_data *ha =
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+ container_of(work, struct qla_hw_data, nic_core_reset);
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+ scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
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+ uint32_t dev_state = 0;
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+
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+ qla83xx_idc_lock(base_vha, 0);
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+ qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
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+ if (dev_state == QLA8XXX_DEV_FAILED ||
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+ dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
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+ qla83xx_idc_state_handler(base_vha);
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+ qla83xx_idc_unlock(base_vha, 0);
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+}
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+
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+int
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+qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
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+{
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+ int rval = QLA_SUCCESS;
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+ unsigned long heart_beat_wait = jiffies + (1 * HZ);
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+ uint32_t heart_beat_counter1, heart_beat_counter2;
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+
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+ do {
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+ if (time_after(jiffies, heart_beat_wait)) {
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+ ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
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+ "Nic Core f/w is not alive.\n");
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+ rval = QLA_FUNCTION_FAILED;
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+ break;
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+ }
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+
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+ qla83xx_idc_lock(base_vha, 0);
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+ qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
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+ &heart_beat_counter1);
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+ qla83xx_idc_unlock(base_vha, 0);
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+ msleep(100);
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+ qla83xx_idc_lock(base_vha, 0);
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+ qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
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+ &heart_beat_counter2);
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+ qla83xx_idc_unlock(base_vha, 0);
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+ } while (heart_beat_counter1 == heart_beat_counter2);
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+
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+ return rval;
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+}
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+
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+/* Work: Perform NIC Core Reset handling */
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+void
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+qla83xx_nic_core_reset_work(struct work_struct *work)
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+{
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+ struct qla_hw_data *ha =
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+ container_of(work, struct qla_hw_data, nic_core_reset);
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+ scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
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+ uint32_t dev_state = 0;
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+
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+ if (!ha->flags.nic_core_reset_hdlr_active) {
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+ if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
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+ qla83xx_idc_lock(base_vha, 0);
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+ qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
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+ &dev_state);
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+ qla83xx_idc_unlock(base_vha, 0);
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+ if (dev_state != QLA8XXX_DEV_NEED_RESET) {
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+ ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
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+ "Nic Core f/w is alive.\n");
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+ return;
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+ }
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+ }
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+
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+ ha->flags.nic_core_reset_hdlr_active = 1;
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+ if (qla83xx_nic_core_reset(base_vha)) {
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+ /* NIC Core reset failed. */
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+ ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
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+ "NIC Core reset failed.\n");
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+ }
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+ ha->flags.nic_core_reset_hdlr_active = 0;
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+ }
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+}
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+
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+/* Work: Handle 8200 IDC aens */
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+void
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+qla83xx_service_idc_aen(struct work_struct *work)
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+{
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+ struct qla_hw_data *ha =
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+ container_of(work, struct qla_hw_data, idc_aen);
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+ scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
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+ uint32_t dev_state, idc_control;
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+
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+ qla83xx_idc_lock(base_vha, 0);
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+ qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
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+ qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
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+ qla83xx_idc_unlock(base_vha, 0);
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+ if (dev_state == QLA8XXX_DEV_NEED_RESET) {
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+ if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
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+ ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
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+ "Application requested NIC Core Reset.\n");
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+ qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
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+ } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
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+ QLA_SUCCESS) {
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+ ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
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+ "Other protocol driver requested NIC Core Reset.\n");
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+ qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
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+ }
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+ } else if (dev_state == QLA8XXX_DEV_FAILED ||
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+ dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
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+ qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
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+ }
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+}
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+
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+static void
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+qla83xx_wait_logic(void)
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+{
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+ int i;
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+
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+ /* Yield CPU */
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+ if (!in_interrupt()) {
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+ /*
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+ * Wait about 200ms before retrying again.
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+ * This controls the number of retries for single
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+ * lock operation.
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+ */
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+ msleep(100);
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+ schedule();
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+ } else {
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+ for (i = 0; i < 20; i++)
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+ cpu_relax(); /* This a nop instr on i386 */
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+ }
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+}
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+
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+int
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+qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
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+{
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+ int rval;
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+ uint32_t data;
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+ uint32_t idc_lck_rcvry_stage_mask = 0x3;
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+ uint32_t idc_lck_rcvry_owner_mask = 0x3c;
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+ struct qla_hw_data *ha = base_vha->hw;
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+
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+ rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
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+ if (rval)
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+ return rval;
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+
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+ if ((data & idc_lck_rcvry_stage_mask) > 0) {
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+ return QLA_SUCCESS;
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+ } else {
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+ data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
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+ rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
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+ data);
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+ if (rval)
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+ return rval;
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+
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+ msleep(200);
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+
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+ rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
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+ &data);
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+ if (rval)
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+ return rval;
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+
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+ if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
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+ data &= (IDC_LOCK_RECOVERY_STAGE2 |
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+ ~(idc_lck_rcvry_stage_mask));
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+ rval = qla83xx_wr_reg(base_vha,
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+ QLA83XX_IDC_LOCK_RECOVERY, data);
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+ if (rval)
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+ return rval;
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+
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+ /* Forcefully perform IDC UnLock */
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+ rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
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+ &data);
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+ if (rval)
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+ return rval;
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+ /* Clear lock-id by setting 0xff */
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+ rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
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+ 0xff);
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+ if (rval)
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+ return rval;
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+ /* Clear lock-recovery by setting 0x0 */
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+ rval = qla83xx_wr_reg(base_vha,
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+ QLA83XX_IDC_LOCK_RECOVERY, 0x0);
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+ if (rval)
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+ return rval;
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+ } else
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+ return QLA_SUCCESS;
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+ }
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+
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+ return rval;
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+}
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+
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+int
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+qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
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+{
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+ int rval = QLA_SUCCESS;
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|
+ uint32_t o_drv_lockid, n_drv_lockid;
|
|
|
+ unsigned long lock_recovery_timeout;
|
|
|
+
|
|
|
+ lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
|
|
|
+retry_lockid:
|
|
|
+ rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
|
|
|
+ if (rval)
|
|
|
+ goto exit;
|
|
|
+
|
|
|
+ /* MAX wait time before forcing IDC Lock recovery = 2 secs */
|
|
|
+ if (time_after_eq(jiffies, lock_recovery_timeout)) {
|
|
|
+ if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
|
|
|
+ return QLA_SUCCESS;
|
|
|
+ else
|
|
|
+ return QLA_FUNCTION_FAILED;
|
|
|
+ }
|
|
|
+
|
|
|
+ rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
|
|
|
+ if (rval)
|
|
|
+ goto exit;
|
|
|
+
|
|
|
+ if (o_drv_lockid == n_drv_lockid) {
|
|
|
+ qla83xx_wait_logic();
|
|
|
+ goto retry_lockid;
|
|
|
+ } else
|
|
|
+ return QLA_SUCCESS;
|
|
|
+
|
|
|
+exit:
|
|
|
+ return rval;
|
|
|
+}
|
|
|
+
|
|
|
+void
|
|
|
+qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
|
|
|
+{
|
|
|
+ uint16_t options = (requester_id << 15) | BIT_6;
|
|
|
+ uint32_t data;
|
|
|
+ struct qla_hw_data *ha = base_vha->hw;
|
|
|
+
|
|
|
+ /* IDC-lock implementation using driver-lock/lock-id remote registers */
|
|
|
+retry_lock:
|
|
|
+ if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
|
|
|
+ == QLA_SUCCESS) {
|
|
|
+ if (data) {
|
|
|
+ /* Setting lock-id to our function-number */
|
|
|
+ qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
|
|
|
+ ha->portnum);
|
|
|
+ } else {
|
|
|
+ ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
|
|
|
+ "Failed to acquire IDC lock. retrying...\n");
|
|
|
+
|
|
|
+ /* Retry/Perform IDC-Lock recovery */
|
|
|
+ if (qla83xx_idc_lock_recovery(base_vha)
|
|
|
+ == QLA_SUCCESS) {
|
|
|
+ qla83xx_wait_logic();
|
|
|
+ goto retry_lock;
|
|
|
+ } else
|
|
|
+ ql_log(ql_log_warn, base_vha, 0xb075,
|
|
|
+ "IDC Lock recovery FAILED.\n");
|
|
|
+ }
|
|
|
+
|
|
|
+ }
|
|
|
+
|
|
|
+ return;
|
|
|
+
|
|
|
+ /* XXX: IDC-lock implementation using access-control mbx */
|
|
|
+retry_lock2:
|
|
|
+ if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
|
|
|
+ ql_dbg(ql_dbg_p3p, base_vha, 0xb072,
|
|
|
+ "Failed to acquire IDC lock. retrying...\n");
|
|
|
+ /* Retry/Perform IDC-Lock recovery */
|
|
|
+ if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) {
|
|
|
+ qla83xx_wait_logic();
|
|
|
+ goto retry_lock2;
|
|
|
+ } else
|
|
|
+ ql_log(ql_log_warn, base_vha, 0xb076,
|
|
|
+ "IDC Lock recovery FAILED.\n");
|
|
|
+ }
|
|
|
+
|
|
|
+ return;
|
|
|
+}
|
|
|
+
|
|
|
+void
|
|
|
+qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
|
|
|
+{
|
|
|
+ uint16_t options = (requester_id << 15) | BIT_7, retry;
|
|
|
+ uint32_t data;
|
|
|
+ struct qla_hw_data *ha = base_vha->hw;
|
|
|
+
|
|
|
+ /* IDC-unlock implementation using driver-unlock/lock-id
|
|
|
+ * remote registers
|
|
|
+ */
|
|
|
+ retry = 0;
|
|
|
+retry_unlock:
|
|
|
+ if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
|
|
|
+ == QLA_SUCCESS) {
|
|
|
+ if (data == ha->portnum) {
|
|
|
+ qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
|
|
|
+ /* Clearing lock-id by setting 0xff */
|
|
|
+ qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
|
|
|
+ } else if (retry < 10) {
|
|
|
+ /* SV: XXX: IDC unlock retrying needed here? */
|
|
|
+
|
|
|
+ /* Retry for IDC-unlock */
|
|
|
+ qla83xx_wait_logic();
|
|
|
+ retry++;
|
|
|
+ ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
|
|
|
+ "Failed to release IDC lock, retyring=%d\n", retry);
|
|
|
+ goto retry_unlock;
|
|
|
+ }
|
|
|
+ } else if (retry < 10) {
|
|
|
+ /* Retry for IDC-unlock */
|
|
|
+ qla83xx_wait_logic();
|
|
|
+ retry++;
|
|
|
+ ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
|
|
|
+ "Failed to read drv-lockid, retyring=%d\n", retry);
|
|
|
+ goto retry_unlock;
|
|
|
+ }
|
|
|
+
|
|
|
+ return;
|
|
|
+
|
|
|
+ /* XXX: IDC-unlock implementation using access-control mbx */
|
|
|
+ retry = 0;
|
|
|
+retry_unlock2:
|
|
|
+ if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
|
|
|
+ if (retry < 10) {
|
|
|
+ /* Retry for IDC-unlock */
|
|
|
+ qla83xx_wait_logic();
|
|
|
+ retry++;
|
|
|
+ ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
|
|
|
+ "Failed to release IDC lock, retyring=%d\n", retry);
|
|
|
+ goto retry_unlock2;
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ return;
|
|
|
+}
|
|
|
+
|
|
|
+int
|
|
|
+__qla83xx_set_drv_presence(scsi_qla_host_t *vha)
|
|
|
+{
|
|
|
+ int rval = QLA_SUCCESS;
|
|
|
+ struct qla_hw_data *ha = vha->hw;
|
|
|
+ uint32_t drv_presence;
|
|
|
+
|
|
|
+ rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
|
|
|
+ if (rval == QLA_SUCCESS) {
|
|
|
+ drv_presence |= (1 << ha->portnum);
|
|
|
+ rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
|
|
|
+ drv_presence);
|
|
|
+ }
|
|
|
+
|
|
|
+ return rval;
|
|
|
+}
|
|
|
+
|
|
|
+int
|
|
|
+qla83xx_set_drv_presence(scsi_qla_host_t *vha)
|
|
|
+{
|
|
|
+ int rval = QLA_SUCCESS;
|
|
|
+
|
|
|
+ qla83xx_idc_lock(vha, 0);
|
|
|
+ rval = __qla83xx_set_drv_presence(vha);
|
|
|
+ qla83xx_idc_unlock(vha, 0);
|
|
|
+
|
|
|
+ return rval;
|
|
|
+}
|
|
|
+
|
|
|
+int
|
|
|
+__qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
|
|
|
+{
|
|
|
+ int rval = QLA_SUCCESS;
|
|
|
+ struct qla_hw_data *ha = vha->hw;
|
|
|
+ uint32_t drv_presence;
|
|
|
+
|
|
|
+ rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
|
|
|
+ if (rval == QLA_SUCCESS) {
|
|
|
+ drv_presence &= ~(1 << ha->portnum);
|
|
|
+ rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
|
|
|
+ drv_presence);
|
|
|
+ }
|
|
|
+
|
|
|
+ return rval;
|
|
|
+}
|
|
|
+
|
|
|
+int
|
|
|
+qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
|
|
|
+{
|
|
|
+ int rval = QLA_SUCCESS;
|
|
|
+
|
|
|
+ qla83xx_idc_lock(vha, 0);
|
|
|
+ rval = __qla83xx_clear_drv_presence(vha);
|
|
|
+ qla83xx_idc_unlock(vha, 0);
|
|
|
+
|
|
|
+ return rval;
|
|
|
+}
|
|
|
+
|
|
|
+void
|
|
|
+qla83xx_need_reset_handler(scsi_qla_host_t *vha)
|
|
|
+{
|
|
|
+ struct qla_hw_data *ha = vha->hw;
|
|
|
+ uint32_t drv_ack, drv_presence;
|
|
|
+ unsigned long ack_timeout;
|
|
|
+
|
|
|
+ /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
|
|
|
+ ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
|
|
|
+ while (1) {
|
|
|
+ qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
|
|
|
+ qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
|
|
|
+ if (drv_ack == drv_presence)
|
|
|
+ break;
|
|
|
+
|
|
|
+ if (time_after_eq(jiffies, ack_timeout)) {
|
|
|
+ ql_log(ql_log_warn, vha, 0xb067,
|
|
|
+ "RESET ACK TIMEOUT! drv_presence=0x%x "
|
|
|
+ "drv_ack=0x%x\n", drv_presence, drv_ack);
|
|
|
+ /*
|
|
|
+ * The function(s) which did not ack in time are forced
|
|
|
+ * to withdraw any further participation in the IDC
|
|
|
+ * reset.
|
|
|
+ */
|
|
|
+ if (drv_ack != drv_presence)
|
|
|
+ qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
|
|
|
+ drv_ack);
|
|
|
+ break;
|
|
|
+ }
|
|
|
+
|
|
|
+ qla83xx_idc_unlock(vha, 0);
|
|
|
+ msleep(1000);
|
|
|
+ qla83xx_idc_lock(vha, 0);
|
|
|
+ }
|
|
|
+
|
|
|
+ qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
|
|
|
+ ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
|
|
|
+}
|
|
|
+
|
|
|
+int
|
|
|
+qla83xx_device_bootstrap(scsi_qla_host_t *vha)
|
|
|
+{
|
|
|
+ int rval = QLA_SUCCESS;
|
|
|
+ uint32_t idc_control;
|
|
|
+
|
|
|
+ qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
|
|
|
+ ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
|
|
|
+
|
|
|
+ /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
|
|
|
+ __qla83xx_get_idc_control(vha, &idc_control);
|
|
|
+ idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
|
|
|
+ __qla83xx_set_idc_control(vha, 0);
|
|
|
+
|
|
|
+ qla83xx_idc_unlock(vha, 0);
|
|
|
+ rval = qla83xx_restart_nic_firmware(vha);
|
|
|
+ qla83xx_idc_lock(vha, 0);
|
|
|
+
|
|
|
+ if (rval != QLA_SUCCESS) {
|
|
|
+ ql_log(ql_log_fatal, vha, 0xb06a,
|
|
|
+ "Failed to restart NIC f/w.\n");
|
|
|
+ qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
|
|
|
+ ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
|
|
|
+ } else {
|
|
|
+ ql_dbg(ql_dbg_p3p, vha, 0xb06c,
|
|
|
+ "Success in restarting nic f/w.\n");
|
|
|
+ qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
|
|
|
+ ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
|
|
|
+ }
|
|
|
+
|
|
|
+ return rval;
|
|
|
+}
|
|
|
+
|
|
|
+/* Assumes idc_lock always held on entry */
|
|
|
+int
|
|
|
+qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
|
|
|
+{
|
|
|
+ struct qla_hw_data *ha = base_vha->hw;
|
|
|
+ int rval = QLA_SUCCESS;
|
|
|
+ unsigned long dev_init_timeout;
|
|
|
+ uint32_t dev_state;
|
|
|
+
|
|
|
+ /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
|
|
|
+ dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
|
|
|
+
|
|
|
+ while (1) {
|
|
|
+
|
|
|
+ if (time_after_eq(jiffies, dev_init_timeout)) {
|
|
|
+ ql_log(ql_log_warn, base_vha, 0xb06e,
|
|
|
+ "Initialization TIMEOUT!\n");
|
|
|
+ /* Init timeout. Disable further NIC Core
|
|
|
+ * communication.
|
|
|
+ */
|
|
|
+ qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
|
|
|
+ QLA8XXX_DEV_FAILED);
|
|
|
+ ql_log(ql_log_info, base_vha, 0xb06f,
|
|
|
+ "HW State: FAILED.\n");
|
|
|
+ }
|
|
|
+
|
|
|
+ qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
|
|
|
+ switch (dev_state) {
|
|
|
+ case QLA8XXX_DEV_READY:
|
|
|
+ if (ha->flags.nic_core_reset_owner)
|
|
|
+ qla83xx_idc_audit(base_vha,
|
|
|
+ IDC_AUDIT_COMPLETION);
|
|
|
+ ha->flags.nic_core_reset_owner = 0;
|
|
|
+ ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
|
|
|
+ "Reset_owner reset by 0x%x.\n",
|
|
|
+ ha->portnum);
|
|
|
+ goto exit;
|
|
|
+ case QLA8XXX_DEV_COLD:
|
|
|
+ if (ha->flags.nic_core_reset_owner)
|
|
|
+ rval = qla83xx_device_bootstrap(base_vha);
|
|
|
+ else {
|
|
|
+ /* Wait for AEN to change device-state */
|
|
|
+ qla83xx_idc_unlock(base_vha, 0);
|
|
|
+ msleep(1000);
|
|
|
+ qla83xx_idc_lock(base_vha, 0);
|
|
|
+ }
|
|
|
+ break;
|
|
|
+ case QLA8XXX_DEV_INITIALIZING:
|
|
|
+ /* Wait for AEN to change device-state */
|
|
|
+ qla83xx_idc_unlock(base_vha, 0);
|
|
|
+ msleep(1000);
|
|
|
+ qla83xx_idc_lock(base_vha, 0);
|
|
|
+ break;
|
|
|
+ case QLA8XXX_DEV_NEED_RESET:
|
|
|
+ if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
|
|
|
+ qla83xx_need_reset_handler(base_vha);
|
|
|
+ else {
|
|
|
+ /* Wait for AEN to change device-state */
|
|
|
+ qla83xx_idc_unlock(base_vha, 0);
|
|
|
+ msleep(1000);
|
|
|
+ qla83xx_idc_lock(base_vha, 0);
|
|
|
+ }
|
|
|
+ /* reset timeout value after need reset handler */
|
|
|
+ dev_init_timeout = jiffies +
|
|
|
+ (ha->fcoe_dev_init_timeout * HZ);
|
|
|
+ break;
|
|
|
+ case QLA8XXX_DEV_NEED_QUIESCENT:
|
|
|
+ /* XXX: DEBUG for now */
|
|
|
+ qla83xx_idc_unlock(base_vha, 0);
|
|
|
+ msleep(1000);
|
|
|
+ qla83xx_idc_lock(base_vha, 0);
|
|
|
+ break;
|
|
|
+ case QLA8XXX_DEV_QUIESCENT:
|
|
|
+ /* XXX: DEBUG for now */
|
|
|
+ if (ha->flags.quiesce_owner)
|
|
|
+ goto exit;
|
|
|
+
|
|
|
+ qla83xx_idc_unlock(base_vha, 0);
|
|
|
+ msleep(1000);
|
|
|
+ qla83xx_idc_lock(base_vha, 0);
|
|
|
+ dev_init_timeout = jiffies +
|
|
|
+ (ha->fcoe_dev_init_timeout * HZ);
|
|
|
+ break;
|
|
|
+ case QLA8XXX_DEV_FAILED:
|
|
|
+ if (ha->flags.nic_core_reset_owner)
|
|
|
+ qla83xx_idc_audit(base_vha,
|
|
|
+ IDC_AUDIT_COMPLETION);
|
|
|
+ ha->flags.nic_core_reset_owner = 0;
|
|
|
+ __qla83xx_clear_drv_presence(base_vha);
|
|
|
+ qla83xx_idc_unlock(base_vha, 0);
|
|
|
+ qla8xxx_dev_failed_handler(base_vha);
|
|
|
+ rval = QLA_FUNCTION_FAILED;
|
|
|
+ qla83xx_idc_lock(base_vha, 0);
|
|
|
+ goto exit;
|
|
|
+ case QLA8XXX_BAD_VALUE:
|
|
|
+ qla83xx_idc_unlock(base_vha, 0);
|
|
|
+ msleep(1000);
|
|
|
+ qla83xx_idc_lock(base_vha, 0);
|
|
|
+ break;
|
|
|
+ default:
|
|
|
+ ql_log(ql_log_warn, base_vha, 0xb071,
|
|
|
+ "Unknow Device State: %x.\n", dev_state);
|
|
|
+ qla83xx_idc_unlock(base_vha, 0);
|
|
|
+ qla8xxx_dev_failed_handler(base_vha);
|
|
|
+ rval = QLA_FUNCTION_FAILED;
|
|
|
+ qla83xx_idc_lock(base_vha, 0);
|
|
|
+ goto exit;
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+exit:
|
|
|
+ return rval;
|
|
|
+}
|
|
|
+
|
|
|
/**************************************************************************
|
|
|
* qla2x00_do_dpc
|
|
|
* This kernel thread is a task that is schedule by the interrupt handler
|
|
|
@@ -3764,7 +4432,7 @@ qla2x00_do_dpc(void *data)
|
|
|
&base_vha->dpc_flags)) {
|
|
|
qla82xx_idc_lock(ha);
|
|
|
qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
|
|
|
- QLA82XX_DEV_FAILED);
|
|
|
+ QLA8XXX_DEV_FAILED);
|
|
|
qla82xx_idc_unlock(ha);
|
|
|
ql_log(ql_log_info, base_vha, 0x4004,
|
|
|
"HW State: FAILED.\n");
|
|
|
@@ -4341,7 +5009,7 @@ uint32_t qla82xx_error_recovery(scsi_qla_host_t *base_vha)
|
|
|
qla82xx_idc_lock(ha);
|
|
|
|
|
|
qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
|
|
|
- QLA82XX_DEV_INITIALIZING);
|
|
|
+ QLA8XXX_DEV_INITIALIZING);
|
|
|
|
|
|
qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
|
|
|
QLA82XX_IDC_VERSION);
|
|
|
@@ -4365,12 +5033,12 @@ uint32_t qla82xx_error_recovery(scsi_qla_host_t *base_vha)
|
|
|
"HW State: FAILED.\n");
|
|
|
qla82xx_clear_drv_active(ha);
|
|
|
qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
|
|
|
- QLA82XX_DEV_FAILED);
|
|
|
+ QLA8XXX_DEV_FAILED);
|
|
|
} else {
|
|
|
ql_log(ql_log_info, base_vha, 0x900c,
|
|
|
"HW State: READY.\n");
|
|
|
qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
|
|
|
- QLA82XX_DEV_READY);
|
|
|
+ QLA8XXX_DEV_READY);
|
|
|
qla82xx_idc_unlock(ha);
|
|
|
ha->flags.isp82xx_fw_hung = 0;
|
|
|
rval = qla82xx_restart_isp(base_vha);
|
|
|
@@ -4385,7 +5053,7 @@ uint32_t qla82xx_error_recovery(scsi_qla_host_t *base_vha)
|
|
|
"This devfn is not reset owner = 0x%x.\n",
|
|
|
ha->pdev->devfn);
|
|
|
if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
|
|
|
- QLA82XX_DEV_READY)) {
|
|
|
+ QLA8XXX_DEV_READY)) {
|
|
|
ha->flags.isp82xx_fw_hung = 0;
|
|
|
rval = qla82xx_restart_isp(base_vha);
|
|
|
qla82xx_idc_lock(ha);
|
Santosh Vernekar