qla_isr.c 80 KB

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  1. /*
  2. * QLogic Fibre Channel HBA Driver
  3. * Copyright (c) 2003-2011 QLogic Corporation
  4. *
  5. * See LICENSE.qla2xxx for copyright and licensing details.
  6. */
  7. #include "qla_def.h"
  8. #include "qla_target.h"
  9. #include <linux/delay.h>
  10. #include <linux/slab.h>
  11. #include <scsi/scsi_tcq.h>
  12. #include <scsi/scsi_bsg_fc.h>
  13. #include <scsi/scsi_eh.h>
  14. static void qla2x00_mbx_completion(scsi_qla_host_t *, uint16_t);
  15. static void qla2x00_process_completed_request(struct scsi_qla_host *,
  16. struct req_que *, uint32_t);
  17. static void qla2x00_status_entry(scsi_qla_host_t *, struct rsp_que *, void *);
  18. static void qla2x00_status_cont_entry(struct rsp_que *, sts_cont_entry_t *);
  19. static void qla2x00_error_entry(scsi_qla_host_t *, struct rsp_que *,
  20. sts_entry_t *);
  21. /**
  22. * qla2100_intr_handler() - Process interrupts for the ISP2100 and ISP2200.
  23. * @irq:
  24. * @dev_id: SCSI driver HA context
  25. *
  26. * Called by system whenever the host adapter generates an interrupt.
  27. *
  28. * Returns handled flag.
  29. */
  30. irqreturn_t
  31. qla2100_intr_handler(int irq, void *dev_id)
  32. {
  33. scsi_qla_host_t *vha;
  34. struct qla_hw_data *ha;
  35. struct device_reg_2xxx __iomem *reg;
  36. int status;
  37. unsigned long iter;
  38. uint16_t hccr;
  39. uint16_t mb[4];
  40. struct rsp_que *rsp;
  41. unsigned long flags;
  42. rsp = (struct rsp_que *) dev_id;
  43. if (!rsp) {
  44. ql_log(ql_log_info, NULL, 0x505d,
  45. "%s: NULL response queue pointer.\n", __func__);
  46. return (IRQ_NONE);
  47. }
  48. ha = rsp->hw;
  49. reg = &ha->iobase->isp;
  50. status = 0;
  51. spin_lock_irqsave(&ha->hardware_lock, flags);
  52. vha = pci_get_drvdata(ha->pdev);
  53. for (iter = 50; iter--; ) {
  54. hccr = RD_REG_WORD(&reg->hccr);
  55. if (hccr & HCCR_RISC_PAUSE) {
  56. if (pci_channel_offline(ha->pdev))
  57. break;
  58. /*
  59. * Issue a "HARD" reset in order for the RISC interrupt
  60. * bit to be cleared. Schedule a big hammer to get
  61. * out of the RISC PAUSED state.
  62. */
  63. WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
  64. RD_REG_WORD(&reg->hccr);
  65. ha->isp_ops->fw_dump(vha, 1);
  66. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  67. break;
  68. } else if ((RD_REG_WORD(&reg->istatus) & ISR_RISC_INT) == 0)
  69. break;
  70. if (RD_REG_WORD(&reg->semaphore) & BIT_0) {
  71. WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
  72. RD_REG_WORD(&reg->hccr);
  73. /* Get mailbox data. */
  74. mb[0] = RD_MAILBOX_REG(ha, reg, 0);
  75. if (mb[0] > 0x3fff && mb[0] < 0x8000) {
  76. qla2x00_mbx_completion(vha, mb[0]);
  77. status |= MBX_INTERRUPT;
  78. } else if (mb[0] > 0x7fff && mb[0] < 0xc000) {
  79. mb[1] = RD_MAILBOX_REG(ha, reg, 1);
  80. mb[2] = RD_MAILBOX_REG(ha, reg, 2);
  81. mb[3] = RD_MAILBOX_REG(ha, reg, 3);
  82. qla2x00_async_event(vha, rsp, mb);
  83. } else {
  84. /*EMPTY*/
  85. ql_dbg(ql_dbg_async, vha, 0x5025,
  86. "Unrecognized interrupt type (%d).\n",
  87. mb[0]);
  88. }
  89. /* Release mailbox registers. */
  90. WRT_REG_WORD(&reg->semaphore, 0);
  91. RD_REG_WORD(&reg->semaphore);
  92. } else {
  93. qla2x00_process_response_queue(rsp);
  94. WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
  95. RD_REG_WORD(&reg->hccr);
  96. }
  97. }
  98. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  99. if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) &&
  100. (status & MBX_INTERRUPT) && ha->flags.mbox_int) {
  101. set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  102. complete(&ha->mbx_intr_comp);
  103. }
  104. return (IRQ_HANDLED);
  105. }
  106. /**
  107. * qla2300_intr_handler() - Process interrupts for the ISP23xx and ISP63xx.
  108. * @irq:
  109. * @dev_id: SCSI driver HA context
  110. *
  111. * Called by system whenever the host adapter generates an interrupt.
  112. *
  113. * Returns handled flag.
  114. */
  115. irqreturn_t
  116. qla2300_intr_handler(int irq, void *dev_id)
  117. {
  118. scsi_qla_host_t *vha;
  119. struct device_reg_2xxx __iomem *reg;
  120. int status;
  121. unsigned long iter;
  122. uint32_t stat;
  123. uint16_t hccr;
  124. uint16_t mb[4];
  125. struct rsp_que *rsp;
  126. struct qla_hw_data *ha;
  127. unsigned long flags;
  128. rsp = (struct rsp_que *) dev_id;
  129. if (!rsp) {
  130. ql_log(ql_log_info, NULL, 0x5058,
  131. "%s: NULL response queue pointer.\n", __func__);
  132. return (IRQ_NONE);
  133. }
  134. ha = rsp->hw;
  135. reg = &ha->iobase->isp;
  136. status = 0;
  137. spin_lock_irqsave(&ha->hardware_lock, flags);
  138. vha = pci_get_drvdata(ha->pdev);
  139. for (iter = 50; iter--; ) {
  140. stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
  141. if (stat & HSR_RISC_PAUSED) {
  142. if (unlikely(pci_channel_offline(ha->pdev)))
  143. break;
  144. hccr = RD_REG_WORD(&reg->hccr);
  145. if (hccr & (BIT_15 | BIT_13 | BIT_11 | BIT_8))
  146. ql_log(ql_log_warn, vha, 0x5026,
  147. "Parity error -- HCCR=%x, Dumping "
  148. "firmware.\n", hccr);
  149. else
  150. ql_log(ql_log_warn, vha, 0x5027,
  151. "RISC paused -- HCCR=%x, Dumping "
  152. "firmware.\n", hccr);
  153. /*
  154. * Issue a "HARD" reset in order for the RISC
  155. * interrupt bit to be cleared. Schedule a big
  156. * hammer to get out of the RISC PAUSED state.
  157. */
  158. WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
  159. RD_REG_WORD(&reg->hccr);
  160. ha->isp_ops->fw_dump(vha, 1);
  161. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  162. break;
  163. } else if ((stat & HSR_RISC_INT) == 0)
  164. break;
  165. switch (stat & 0xff) {
  166. case 0x1:
  167. case 0x2:
  168. case 0x10:
  169. case 0x11:
  170. qla2x00_mbx_completion(vha, MSW(stat));
  171. status |= MBX_INTERRUPT;
  172. /* Release mailbox registers. */
  173. WRT_REG_WORD(&reg->semaphore, 0);
  174. break;
  175. case 0x12:
  176. mb[0] = MSW(stat);
  177. mb[1] = RD_MAILBOX_REG(ha, reg, 1);
  178. mb[2] = RD_MAILBOX_REG(ha, reg, 2);
  179. mb[3] = RD_MAILBOX_REG(ha, reg, 3);
  180. qla2x00_async_event(vha, rsp, mb);
  181. break;
  182. case 0x13:
  183. qla2x00_process_response_queue(rsp);
  184. break;
  185. case 0x15:
  186. mb[0] = MBA_CMPLT_1_16BIT;
  187. mb[1] = MSW(stat);
  188. qla2x00_async_event(vha, rsp, mb);
  189. break;
  190. case 0x16:
  191. mb[0] = MBA_SCSI_COMPLETION;
  192. mb[1] = MSW(stat);
  193. mb[2] = RD_MAILBOX_REG(ha, reg, 2);
  194. qla2x00_async_event(vha, rsp, mb);
  195. break;
  196. default:
  197. ql_dbg(ql_dbg_async, vha, 0x5028,
  198. "Unrecognized interrupt type (%d).\n", stat & 0xff);
  199. break;
  200. }
  201. WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
  202. RD_REG_WORD_RELAXED(&reg->hccr);
  203. }
  204. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  205. if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) &&
  206. (status & MBX_INTERRUPT) && ha->flags.mbox_int) {
  207. set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  208. complete(&ha->mbx_intr_comp);
  209. }
  210. return (IRQ_HANDLED);
  211. }
  212. /**
  213. * qla2x00_mbx_completion() - Process mailbox command completions.
  214. * @ha: SCSI driver HA context
  215. * @mb0: Mailbox0 register
  216. */
  217. static void
  218. qla2x00_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0)
  219. {
  220. uint16_t cnt;
  221. uint32_t mboxes;
  222. uint16_t __iomem *wptr;
  223. struct qla_hw_data *ha = vha->hw;
  224. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  225. /* Read all mbox registers? */
  226. mboxes = (1 << ha->mbx_count) - 1;
  227. if (!ha->mcp)
  228. ql_dbg(ql_dbg_async, vha, 0x5001, "MBX pointer ERRROR.\n");
  229. else
  230. mboxes = ha->mcp->in_mb;
  231. /* Load return mailbox registers. */
  232. ha->flags.mbox_int = 1;
  233. ha->mailbox_out[0] = mb0;
  234. mboxes >>= 1;
  235. wptr = (uint16_t __iomem *)MAILBOX_REG(ha, reg, 1);
  236. for (cnt = 1; cnt < ha->mbx_count; cnt++) {
  237. if (IS_QLA2200(ha) && cnt == 8)
  238. wptr = (uint16_t __iomem *)MAILBOX_REG(ha, reg, 8);
  239. if ((cnt == 4 || cnt == 5) && (mboxes & BIT_0))
  240. ha->mailbox_out[cnt] = qla2x00_debounce_register(wptr);
  241. else if (mboxes & BIT_0)
  242. ha->mailbox_out[cnt] = RD_REG_WORD(wptr);
  243. wptr++;
  244. mboxes >>= 1;
  245. }
  246. }
  247. static void
  248. qla81xx_idc_event(scsi_qla_host_t *vha, uint16_t aen, uint16_t descr)
  249. {
  250. static char *event[] =
  251. { "Complete", "Request Notification", "Time Extension" };
  252. int rval;
  253. struct device_reg_24xx __iomem *reg24 = &vha->hw->iobase->isp24;
  254. uint16_t __iomem *wptr;
  255. uint16_t cnt, timeout, mb[QLA_IDC_ACK_REGS];
  256. /* Seed data -- mailbox1 -> mailbox7. */
  257. wptr = (uint16_t __iomem *)&reg24->mailbox1;
  258. for (cnt = 0; cnt < QLA_IDC_ACK_REGS; cnt++, wptr++)
  259. mb[cnt] = RD_REG_WORD(wptr);
  260. ql_dbg(ql_dbg_async, vha, 0x5021,
  261. "Inter-Driver Communication %s -- "
  262. "%04x %04x %04x %04x %04x %04x %04x.\n",
  263. event[aen & 0xff], mb[0], mb[1], mb[2], mb[3],
  264. mb[4], mb[5], mb[6]);
  265. /* Acknowledgement needed? [Notify && non-zero timeout]. */
  266. timeout = (descr >> 8) & 0xf;
  267. if (aen != MBA_IDC_NOTIFY || !timeout)
  268. return;
  269. ql_dbg(ql_dbg_async, vha, 0x5022,
  270. "%lu Inter-Driver Communication %s -- ACK timeout=%d.\n",
  271. vha->host_no, event[aen & 0xff], timeout);
  272. rval = qla2x00_post_idc_ack_work(vha, mb);
  273. if (rval != QLA_SUCCESS)
  274. ql_log(ql_log_warn, vha, 0x5023,
  275. "IDC failed to post ACK.\n");
  276. }
  277. #define LS_UNKNOWN 2
  278. char *
  279. qla2x00_get_link_speed_str(struct qla_hw_data *ha)
  280. {
  281. static char *link_speeds[] = {"1", "2", "?", "4", "8", "16", "10"};
  282. char *link_speed;
  283. int fw_speed = ha->link_data_rate;
  284. if (IS_QLA2100(ha) || IS_QLA2200(ha))
  285. link_speed = link_speeds[0];
  286. else if (fw_speed == 0x13)
  287. link_speed = link_speeds[6];
  288. else {
  289. link_speed = link_speeds[LS_UNKNOWN];
  290. if (fw_speed < 6)
  291. link_speed =
  292. link_speeds[fw_speed];
  293. }
  294. return link_speed;
  295. }
  296. void
  297. qla83xx_handle_8200_aen(scsi_qla_host_t *vha, uint16_t *mb)
  298. {
  299. struct qla_hw_data *ha = vha->hw;
  300. /*
  301. * 8200 AEN Interpretation:
  302. * mb[0] = AEN code
  303. * mb[1] = AEN Reason code
  304. * mb[2] = LSW of Peg-Halt Status-1 Register
  305. * mb[6] = MSW of Peg-Halt Status-1 Register
  306. * mb[3] = LSW of Peg-Halt Status-2 register
  307. * mb[7] = MSW of Peg-Halt Status-2 register
  308. * mb[4] = IDC Device-State Register value
  309. * mb[5] = IDC Driver-Presence Register value
  310. */
  311. ql_dbg(ql_dbg_async, vha, 0x506b, "AEN Code: mb[0] = 0x%x AEN reason: "
  312. "mb[1] = 0x%x PH-status1: mb[2] = 0x%x PH-status1: mb[6] = 0x%x.\n",
  313. mb[0], mb[1], mb[2], mb[6]);
  314. ql_dbg(ql_dbg_async, vha, 0x506c, "PH-status2: mb[3] = 0x%x "
  315. "PH-status2: mb[7] = 0x%x Device-State: mb[4] = 0x%x "
  316. "Drv-Presence: mb[5] = 0x%x.\n", mb[3], mb[7], mb[4], mb[5]);
  317. if (mb[1] & (IDC_PEG_HALT_STATUS_CHANGE | IDC_NIC_FW_REPORTED_FAILURE |
  318. IDC_HEARTBEAT_FAILURE)) {
  319. ha->flags.nic_core_hung = 1;
  320. ql_log(ql_log_warn, vha, 0x5060,
  321. "83XX: F/W Error Reported: Check if reset required.\n");
  322. if (mb[1] & IDC_PEG_HALT_STATUS_CHANGE) {
  323. uint32_t protocol_engine_id, fw_err_code, err_level;
  324. /*
  325. * IDC_PEG_HALT_STATUS_CHANGE interpretation:
  326. * - PEG-Halt Status-1 Register:
  327. * (LSW = mb[2], MSW = mb[6])
  328. * Bits 0-7 = protocol-engine ID
  329. * Bits 8-28 = f/w error code
  330. * Bits 29-31 = Error-level
  331. * Error-level 0x1 = Non-Fatal error
  332. * Error-level 0x2 = Recoverable Fatal error
  333. * Error-level 0x4 = UnRecoverable Fatal error
  334. * - PEG-Halt Status-2 Register:
  335. * (LSW = mb[3], MSW = mb[7])
  336. */
  337. protocol_engine_id = (mb[2] & 0xff);
  338. fw_err_code = (((mb[2] & 0xff00) >> 8) |
  339. ((mb[6] & 0x1fff) << 8));
  340. err_level = ((mb[6] & 0xe000) >> 13);
  341. ql_log(ql_log_warn, vha, 0x5061, "PegHalt Status-1 "
  342. "Register: protocol_engine_id=0x%x "
  343. "fw_err_code=0x%x err_level=0x%x.\n",
  344. protocol_engine_id, fw_err_code, err_level);
  345. ql_log(ql_log_warn, vha, 0x5062, "PegHalt Status-2 "
  346. "Register: 0x%x%x.\n", mb[7], mb[3]);
  347. if (err_level == ERR_LEVEL_NON_FATAL) {
  348. ql_log(ql_log_warn, vha, 0x5063,
  349. "Not a fatal error, f/w has recovered "
  350. "iteself.\n");
  351. } else if (err_level == ERR_LEVEL_RECOVERABLE_FATAL) {
  352. ql_log(ql_log_fatal, vha, 0x5064,
  353. "Recoverable Fatal error: Chip reset "
  354. "required.\n");
  355. qla83xx_schedule_work(vha,
  356. QLA83XX_NIC_CORE_RESET);
  357. } else if (err_level == ERR_LEVEL_UNRECOVERABLE_FATAL) {
  358. ql_log(ql_log_fatal, vha, 0x5065,
  359. "Unrecoverable Fatal error: Set FAILED "
  360. "state, reboot required.\n");
  361. qla83xx_schedule_work(vha,
  362. QLA83XX_NIC_CORE_UNRECOVERABLE);
  363. }
  364. }
  365. if (mb[1] & IDC_NIC_FW_REPORTED_FAILURE) {
  366. uint16_t peg_fw_state, nw_interface_link_up;
  367. uint16_t nw_interface_signal_detect, sfp_status;
  368. uint16_t htbt_counter, htbt_monitor_enable;
  369. uint16_t sfp_additonal_info, sfp_multirate;
  370. uint16_t sfp_tx_fault, link_speed, dcbx_status;
  371. /*
  372. * IDC_NIC_FW_REPORTED_FAILURE interpretation:
  373. * - PEG-to-FC Status Register:
  374. * (LSW = mb[2], MSW = mb[6])
  375. * Bits 0-7 = Peg-Firmware state
  376. * Bit 8 = N/W Interface Link-up
  377. * Bit 9 = N/W Interface signal detected
  378. * Bits 10-11 = SFP Status
  379. * SFP Status 0x0 = SFP+ transceiver not expected
  380. * SFP Status 0x1 = SFP+ transceiver not present
  381. * SFP Status 0x2 = SFP+ transceiver invalid
  382. * SFP Status 0x3 = SFP+ transceiver present and
  383. * valid
  384. * Bits 12-14 = Heartbeat Counter
  385. * Bit 15 = Heartbeat Monitor Enable
  386. * Bits 16-17 = SFP Additional Info
  387. * SFP info 0x0 = Unregocnized transceiver for
  388. * Ethernet
  389. * SFP info 0x1 = SFP+ brand validation failed
  390. * SFP info 0x2 = SFP+ speed validation failed
  391. * SFP info 0x3 = SFP+ access error
  392. * Bit 18 = SFP Multirate
  393. * Bit 19 = SFP Tx Fault
  394. * Bits 20-22 = Link Speed
  395. * Bits 23-27 = Reserved
  396. * Bits 28-30 = DCBX Status
  397. * DCBX Status 0x0 = DCBX Disabled
  398. * DCBX Status 0x1 = DCBX Enabled
  399. * DCBX Status 0x2 = DCBX Exchange error
  400. * Bit 31 = Reserved
  401. */
  402. peg_fw_state = (mb[2] & 0x00ff);
  403. nw_interface_link_up = ((mb[2] & 0x0100) >> 8);
  404. nw_interface_signal_detect = ((mb[2] & 0x0200) >> 9);
  405. sfp_status = ((mb[2] & 0x0c00) >> 10);
  406. htbt_counter = ((mb[2] & 0x7000) >> 12);
  407. htbt_monitor_enable = ((mb[2] & 0x8000) >> 15);
  408. sfp_additonal_info = (mb[6] & 0x0003);
  409. sfp_multirate = ((mb[6] & 0x0004) >> 2);
  410. sfp_tx_fault = ((mb[6] & 0x0008) >> 3);
  411. link_speed = ((mb[6] & 0x0070) >> 4);
  412. dcbx_status = ((mb[6] & 0x7000) >> 12);
  413. ql_log(ql_log_warn, vha, 0x5066,
  414. "Peg-to-Fc Status Register:\n"
  415. "peg_fw_state=0x%x, nw_interface_link_up=0x%x, "
  416. "nw_interface_signal_detect=0x%x"
  417. "\nsfp_statis=0x%x.\n ", peg_fw_state,
  418. nw_interface_link_up, nw_interface_signal_detect,
  419. sfp_status);
  420. ql_log(ql_log_warn, vha, 0x5067,
  421. "htbt_counter=0x%x, htbt_monitor_enable=0x%x, "
  422. "sfp_additonal_info=0x%x, sfp_multirate=0x%x.\n ",
  423. htbt_counter, htbt_monitor_enable,
  424. sfp_additonal_info, sfp_multirate);
  425. ql_log(ql_log_warn, vha, 0x5068,
  426. "sfp_tx_fault=0x%x, link_state=0x%x, "
  427. "dcbx_status=0x%x.\n", sfp_tx_fault, link_speed,
  428. dcbx_status);
  429. qla83xx_schedule_work(vha, QLA83XX_NIC_CORE_RESET);
  430. }
  431. if (mb[1] & IDC_HEARTBEAT_FAILURE) {
  432. ql_log(ql_log_warn, vha, 0x5069,
  433. "Heartbeat Failure encountered, chip reset "
  434. "required.\n");
  435. qla83xx_schedule_work(vha, QLA83XX_NIC_CORE_RESET);
  436. }
  437. }
  438. if (mb[1] & IDC_DEVICE_STATE_CHANGE) {
  439. ql_log(ql_log_info, vha, 0x506a,
  440. "IDC Device-State changed = 0x%x.\n", mb[4]);
  441. qla83xx_schedule_work(vha, MBA_IDC_AEN);
  442. }
  443. }
  444. /**
  445. * qla2x00_async_event() - Process aynchronous events.
  446. * @ha: SCSI driver HA context
  447. * @mb: Mailbox registers (0 - 3)
  448. */
  449. void
  450. qla2x00_async_event(scsi_qla_host_t *vha, struct rsp_que *rsp, uint16_t *mb)
  451. {
  452. uint16_t handle_cnt;
  453. uint16_t cnt, mbx;
  454. uint32_t handles[5];
  455. struct qla_hw_data *ha = vha->hw;
  456. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  457. struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
  458. struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
  459. uint32_t rscn_entry, host_pid;
  460. unsigned long flags;
  461. /* Setup to process RIO completion. */
  462. handle_cnt = 0;
  463. if (IS_CNA_CAPABLE(ha))
  464. goto skip_rio;
  465. switch (mb[0]) {
  466. case MBA_SCSI_COMPLETION:
  467. handles[0] = le32_to_cpu((uint32_t)((mb[2] << 16) | mb[1]));
  468. handle_cnt = 1;
  469. break;
  470. case MBA_CMPLT_1_16BIT:
  471. handles[0] = mb[1];
  472. handle_cnt = 1;
  473. mb[0] = MBA_SCSI_COMPLETION;
  474. break;
  475. case MBA_CMPLT_2_16BIT:
  476. handles[0] = mb[1];
  477. handles[1] = mb[2];
  478. handle_cnt = 2;
  479. mb[0] = MBA_SCSI_COMPLETION;
  480. break;
  481. case MBA_CMPLT_3_16BIT:
  482. handles[0] = mb[1];
  483. handles[1] = mb[2];
  484. handles[2] = mb[3];
  485. handle_cnt = 3;
  486. mb[0] = MBA_SCSI_COMPLETION;
  487. break;
  488. case MBA_CMPLT_4_16BIT:
  489. handles[0] = mb[1];
  490. handles[1] = mb[2];
  491. handles[2] = mb[3];
  492. handles[3] = (uint32_t)RD_MAILBOX_REG(ha, reg, 6);
  493. handle_cnt = 4;
  494. mb[0] = MBA_SCSI_COMPLETION;
  495. break;
  496. case MBA_CMPLT_5_16BIT:
  497. handles[0] = mb[1];
  498. handles[1] = mb[2];
  499. handles[2] = mb[3];
  500. handles[3] = (uint32_t)RD_MAILBOX_REG(ha, reg, 6);
  501. handles[4] = (uint32_t)RD_MAILBOX_REG(ha, reg, 7);
  502. handle_cnt = 5;
  503. mb[0] = MBA_SCSI_COMPLETION;
  504. break;
  505. case MBA_CMPLT_2_32BIT:
  506. handles[0] = le32_to_cpu((uint32_t)((mb[2] << 16) | mb[1]));
  507. handles[1] = le32_to_cpu(
  508. ((uint32_t)(RD_MAILBOX_REG(ha, reg, 7) << 16)) |
  509. RD_MAILBOX_REG(ha, reg, 6));
  510. handle_cnt = 2;
  511. mb[0] = MBA_SCSI_COMPLETION;
  512. break;
  513. default:
  514. break;
  515. }
  516. skip_rio:
  517. switch (mb[0]) {
  518. case MBA_SCSI_COMPLETION: /* Fast Post */
  519. if (!vha->flags.online)
  520. break;
  521. for (cnt = 0; cnt < handle_cnt; cnt++)
  522. qla2x00_process_completed_request(vha, rsp->req,
  523. handles[cnt]);
  524. break;
  525. case MBA_RESET: /* Reset */
  526. ql_dbg(ql_dbg_async, vha, 0x5002,
  527. "Asynchronous RESET.\n");
  528. set_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  529. break;
  530. case MBA_SYSTEM_ERR: /* System Error */
  531. mbx = (IS_QLA81XX(ha) || IS_QLA83XX(ha)) ?
  532. RD_REG_WORD(&reg24->mailbox7) : 0;
  533. ql_log(ql_log_warn, vha, 0x5003,
  534. "ISP System Error - mbx1=%xh mbx2=%xh mbx3=%xh "
  535. "mbx7=%xh.\n", mb[1], mb[2], mb[3], mbx);
  536. ha->isp_ops->fw_dump(vha, 1);
  537. if (IS_FWI2_CAPABLE(ha)) {
  538. if (mb[1] == 0 && mb[2] == 0) {
  539. ql_log(ql_log_fatal, vha, 0x5004,
  540. "Unrecoverable Hardware Error: adapter "
  541. "marked OFFLINE!\n");
  542. vha->flags.online = 0;
  543. vha->device_flags |= DFLG_DEV_FAILED;
  544. } else {
  545. /* Check to see if MPI timeout occurred */
  546. if ((mbx & MBX_3) && (ha->flags.port0))
  547. set_bit(MPI_RESET_NEEDED,
  548. &vha->dpc_flags);
  549. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  550. }
  551. } else if (mb[1] == 0) {
  552. ql_log(ql_log_fatal, vha, 0x5005,
  553. "Unrecoverable Hardware Error: adapter marked "
  554. "OFFLINE!\n");
  555. vha->flags.online = 0;
  556. vha->device_flags |= DFLG_DEV_FAILED;
  557. } else
  558. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  559. break;
  560. case MBA_REQ_TRANSFER_ERR: /* Request Transfer Error */
  561. ql_log(ql_log_warn, vha, 0x5006,
  562. "ISP Request Transfer Error (%x).\n", mb[1]);
  563. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  564. break;
  565. case MBA_RSP_TRANSFER_ERR: /* Response Transfer Error */
  566. ql_log(ql_log_warn, vha, 0x5007,
  567. "ISP Response Transfer Error.\n");
  568. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  569. break;
  570. case MBA_WAKEUP_THRES: /* Request Queue Wake-up */
  571. ql_dbg(ql_dbg_async, vha, 0x5008,
  572. "Asynchronous WAKEUP_THRES.\n");
  573. break;
  574. case MBA_LIP_OCCURRED: /* Loop Initialization Procedure */
  575. ql_dbg(ql_dbg_async, vha, 0x5009,
  576. "LIP occurred (%x).\n", mb[1]);
  577. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  578. atomic_set(&vha->loop_state, LOOP_DOWN);
  579. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  580. qla2x00_mark_all_devices_lost(vha, 1);
  581. }
  582. if (vha->vp_idx) {
  583. atomic_set(&vha->vp_state, VP_FAILED);
  584. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  585. }
  586. set_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags);
  587. set_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags);
  588. vha->flags.management_server_logged_in = 0;
  589. qla2x00_post_aen_work(vha, FCH_EVT_LIP, mb[1]);
  590. break;
  591. case MBA_LOOP_UP: /* Loop Up Event */
  592. if (IS_QLA2100(ha) || IS_QLA2200(ha))
  593. ha->link_data_rate = PORT_SPEED_1GB;
  594. else
  595. ha->link_data_rate = mb[1];
  596. ql_dbg(ql_dbg_async, vha, 0x500a,
  597. "LOOP UP detected (%s Gbps).\n",
  598. qla2x00_get_link_speed_str(ha));
  599. vha->flags.management_server_logged_in = 0;
  600. qla2x00_post_aen_work(vha, FCH_EVT_LINKUP, ha->link_data_rate);
  601. break;
  602. case MBA_LOOP_DOWN: /* Loop Down Event */
  603. mbx = (IS_QLA81XX(ha) || IS_QLA8031(ha))
  604. ? RD_REG_WORD(&reg24->mailbox4) : 0;
  605. mbx = IS_QLA82XX(ha) ? RD_REG_WORD(&reg82->mailbox_out[4]) : mbx;
  606. ql_dbg(ql_dbg_async, vha, 0x500b,
  607. "LOOP DOWN detected (%x %x %x %x).\n",
  608. mb[1], mb[2], mb[3], mbx);
  609. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  610. atomic_set(&vha->loop_state, LOOP_DOWN);
  611. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  612. vha->device_flags |= DFLG_NO_CABLE;
  613. qla2x00_mark_all_devices_lost(vha, 1);
  614. }
  615. if (vha->vp_idx) {
  616. atomic_set(&vha->vp_state, VP_FAILED);
  617. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  618. }
  619. vha->flags.management_server_logged_in = 0;
  620. ha->link_data_rate = PORT_SPEED_UNKNOWN;
  621. qla2x00_post_aen_work(vha, FCH_EVT_LINKDOWN, 0);
  622. break;
  623. case MBA_LIP_RESET: /* LIP reset occurred */
  624. ql_dbg(ql_dbg_async, vha, 0x500c,
  625. "LIP reset occurred (%x).\n", mb[1]);
  626. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  627. atomic_set(&vha->loop_state, LOOP_DOWN);
  628. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  629. qla2x00_mark_all_devices_lost(vha, 1);
  630. }
  631. if (vha->vp_idx) {
  632. atomic_set(&vha->vp_state, VP_FAILED);
  633. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  634. }
  635. set_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  636. ha->operating_mode = LOOP;
  637. vha->flags.management_server_logged_in = 0;
  638. qla2x00_post_aen_work(vha, FCH_EVT_LIPRESET, mb[1]);
  639. break;
  640. /* case MBA_DCBX_COMPLETE: */
  641. case MBA_POINT_TO_POINT: /* Point-to-Point */
  642. if (IS_QLA2100(ha))
  643. break;
  644. if (IS_QLA81XX(ha) || IS_QLA82XX(ha) || IS_QLA8031(ha)) {
  645. ql_dbg(ql_dbg_async, vha, 0x500d,
  646. "DCBX Completed -- %04x %04x %04x.\n",
  647. mb[1], mb[2], mb[3]);
  648. if (ha->notify_dcbx_comp)
  649. complete(&ha->dcbx_comp);
  650. } else
  651. ql_dbg(ql_dbg_async, vha, 0x500e,
  652. "Asynchronous P2P MODE received.\n");
  653. /*
  654. * Until there's a transition from loop down to loop up, treat
  655. * this as loop down only.
  656. */
  657. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  658. atomic_set(&vha->loop_state, LOOP_DOWN);
  659. if (!atomic_read(&vha->loop_down_timer))
  660. atomic_set(&vha->loop_down_timer,
  661. LOOP_DOWN_TIME);
  662. qla2x00_mark_all_devices_lost(vha, 1);
  663. }
  664. if (vha->vp_idx) {
  665. atomic_set(&vha->vp_state, VP_FAILED);
  666. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  667. }
  668. if (!(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)))
  669. set_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  670. set_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags);
  671. set_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags);
  672. ha->flags.gpsc_supported = 1;
  673. vha->flags.management_server_logged_in = 0;
  674. break;
  675. case MBA_CHG_IN_CONNECTION: /* Change in connection mode */
  676. if (IS_QLA2100(ha))
  677. break;
  678. ql_dbg(ql_dbg_async, vha, 0x500f,
  679. "Configuration change detected: value=%x.\n", mb[1]);
  680. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  681. atomic_set(&vha->loop_state, LOOP_DOWN);
  682. if (!atomic_read(&vha->loop_down_timer))
  683. atomic_set(&vha->loop_down_timer,
  684. LOOP_DOWN_TIME);
  685. qla2x00_mark_all_devices_lost(vha, 1);
  686. }
  687. if (vha->vp_idx) {
  688. atomic_set(&vha->vp_state, VP_FAILED);
  689. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  690. }
  691. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  692. set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  693. break;
  694. case MBA_PORT_UPDATE: /* Port database update */
  695. /*
  696. * Handle only global and vn-port update events
  697. *
  698. * Relevant inputs:
  699. * mb[1] = N_Port handle of changed port
  700. * OR 0xffff for global event
  701. * mb[2] = New login state
  702. * 7 = Port logged out
  703. * mb[3] = LSB is vp_idx, 0xff = all vps
  704. *
  705. * Skip processing if:
  706. * Event is global, vp_idx is NOT all vps,
  707. * vp_idx does not match
  708. * Event is not global, vp_idx does not match
  709. */
  710. if (IS_QLA2XXX_MIDTYPE(ha) &&
  711. ((mb[1] == 0xffff && (mb[3] & 0xff) != 0xff) ||
  712. (mb[1] != 0xffff)) && vha->vp_idx != (mb[3] & 0xff))
  713. break;
  714. /* Global event -- port logout or port unavailable. */
  715. if (mb[1] == 0xffff && mb[2] == 0x7) {
  716. ql_dbg(ql_dbg_async, vha, 0x5010,
  717. "Port unavailable %04x %04x %04x.\n",
  718. mb[1], mb[2], mb[3]);
  719. ql_log(ql_log_warn, vha, 0x505e,
  720. "Link is offline.\n");
  721. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  722. atomic_set(&vha->loop_state, LOOP_DOWN);
  723. atomic_set(&vha->loop_down_timer,
  724. LOOP_DOWN_TIME);
  725. vha->device_flags |= DFLG_NO_CABLE;
  726. qla2x00_mark_all_devices_lost(vha, 1);
  727. }
  728. if (vha->vp_idx) {
  729. atomic_set(&vha->vp_state, VP_FAILED);
  730. fc_vport_set_state(vha->fc_vport,
  731. FC_VPORT_FAILED);
  732. qla2x00_mark_all_devices_lost(vha, 1);
  733. }
  734. vha->flags.management_server_logged_in = 0;
  735. ha->link_data_rate = PORT_SPEED_UNKNOWN;
  736. break;
  737. }
  738. /*
  739. * If PORT UPDATE is global (received LIP_OCCURRED/LIP_RESET
  740. * event etc. earlier indicating loop is down) then process
  741. * it. Otherwise ignore it and Wait for RSCN to come in.
  742. */
  743. atomic_set(&vha->loop_down_timer, 0);
  744. if (atomic_read(&vha->loop_state) != LOOP_DOWN &&
  745. atomic_read(&vha->loop_state) != LOOP_DEAD) {
  746. ql_dbg(ql_dbg_async, vha, 0x5011,
  747. "Asynchronous PORT UPDATE ignored %04x/%04x/%04x.\n",
  748. mb[1], mb[2], mb[3]);
  749. qlt_async_event(mb[0], vha, mb);
  750. break;
  751. }
  752. ql_dbg(ql_dbg_async, vha, 0x5012,
  753. "Port database changed %04x %04x %04x.\n",
  754. mb[1], mb[2], mb[3]);
  755. ql_log(ql_log_warn, vha, 0x505f,
  756. "Link is operational (%s Gbps).\n",
  757. qla2x00_get_link_speed_str(ha));
  758. /*
  759. * Mark all devices as missing so we will login again.
  760. */
  761. atomic_set(&vha->loop_state, LOOP_UP);
  762. qla2x00_mark_all_devices_lost(vha, 1);
  763. if (vha->vp_idx == 0 && !qla_ini_mode_enabled(vha))
  764. set_bit(SCR_PENDING, &vha->dpc_flags);
  765. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  766. set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  767. qlt_async_event(mb[0], vha, mb);
  768. break;
  769. case MBA_RSCN_UPDATE: /* State Change Registration */
  770. /* Check if the Vport has issued a SCR */
  771. if (vha->vp_idx && test_bit(VP_SCR_NEEDED, &vha->vp_flags))
  772. break;
  773. /* Only handle SCNs for our Vport index. */
  774. if (ha->flags.npiv_supported && vha->vp_idx != (mb[3] & 0xff))
  775. break;
  776. ql_dbg(ql_dbg_async, vha, 0x5013,
  777. "RSCN database changed -- %04x %04x %04x.\n",
  778. mb[1], mb[2], mb[3]);
  779. rscn_entry = ((mb[1] & 0xff) << 16) | mb[2];
  780. host_pid = (vha->d_id.b.domain << 16) | (vha->d_id.b.area << 8)
  781. | vha->d_id.b.al_pa;
  782. if (rscn_entry == host_pid) {
  783. ql_dbg(ql_dbg_async, vha, 0x5014,
  784. "Ignoring RSCN update to local host "
  785. "port ID (%06x).\n", host_pid);
  786. break;
  787. }
  788. /* Ignore reserved bits from RSCN-payload. */
  789. rscn_entry = ((mb[1] & 0x3ff) << 16) | mb[2];
  790. atomic_set(&vha->loop_down_timer, 0);
  791. vha->flags.management_server_logged_in = 0;
  792. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  793. set_bit(RSCN_UPDATE, &vha->dpc_flags);
  794. qla2x00_post_aen_work(vha, FCH_EVT_RSCN, rscn_entry);
  795. break;
  796. /* case MBA_RIO_RESPONSE: */
  797. case MBA_ZIO_RESPONSE:
  798. ql_dbg(ql_dbg_async, vha, 0x5015,
  799. "[R|Z]IO update completion.\n");
  800. if (IS_FWI2_CAPABLE(ha))
  801. qla24xx_process_response_queue(vha, rsp);
  802. else
  803. qla2x00_process_response_queue(rsp);
  804. break;
  805. case MBA_DISCARD_RND_FRAME:
  806. ql_dbg(ql_dbg_async, vha, 0x5016,
  807. "Discard RND Frame -- %04x %04x %04x.\n",
  808. mb[1], mb[2], mb[3]);
  809. break;
  810. case MBA_TRACE_NOTIFICATION:
  811. ql_dbg(ql_dbg_async, vha, 0x5017,
  812. "Trace Notification -- %04x %04x.\n", mb[1], mb[2]);
  813. break;
  814. case MBA_ISP84XX_ALERT:
  815. ql_dbg(ql_dbg_async, vha, 0x5018,
  816. "ISP84XX Alert Notification -- %04x %04x %04x.\n",
  817. mb[1], mb[2], mb[3]);
  818. spin_lock_irqsave(&ha->cs84xx->access_lock, flags);
  819. switch (mb[1]) {
  820. case A84_PANIC_RECOVERY:
  821. ql_log(ql_log_info, vha, 0x5019,
  822. "Alert 84XX: panic recovery %04x %04x.\n",
  823. mb[2], mb[3]);
  824. break;
  825. case A84_OP_LOGIN_COMPLETE:
  826. ha->cs84xx->op_fw_version = mb[3] << 16 | mb[2];
  827. ql_log(ql_log_info, vha, 0x501a,
  828. "Alert 84XX: firmware version %x.\n",
  829. ha->cs84xx->op_fw_version);
  830. break;
  831. case A84_DIAG_LOGIN_COMPLETE:
  832. ha->cs84xx->diag_fw_version = mb[3] << 16 | mb[2];
  833. ql_log(ql_log_info, vha, 0x501b,
  834. "Alert 84XX: diagnostic firmware version %x.\n",
  835. ha->cs84xx->diag_fw_version);
  836. break;
  837. case A84_GOLD_LOGIN_COMPLETE:
  838. ha->cs84xx->diag_fw_version = mb[3] << 16 | mb[2];
  839. ha->cs84xx->fw_update = 1;
  840. ql_log(ql_log_info, vha, 0x501c,
  841. "Alert 84XX: gold firmware version %x.\n",
  842. ha->cs84xx->gold_fw_version);
  843. break;
  844. default:
  845. ql_log(ql_log_warn, vha, 0x501d,
  846. "Alert 84xx: Invalid Alert %04x %04x %04x.\n",
  847. mb[1], mb[2], mb[3]);
  848. }
  849. spin_unlock_irqrestore(&ha->cs84xx->access_lock, flags);
  850. break;
  851. case MBA_DCBX_START:
  852. ql_dbg(ql_dbg_async, vha, 0x501e,
  853. "DCBX Started -- %04x %04x %04x.\n",
  854. mb[1], mb[2], mb[3]);
  855. break;
  856. case MBA_DCBX_PARAM_UPDATE:
  857. ql_dbg(ql_dbg_async, vha, 0x501f,
  858. "DCBX Parameters Updated -- %04x %04x %04x.\n",
  859. mb[1], mb[2], mb[3]);
  860. break;
  861. case MBA_FCF_CONF_ERR:
  862. ql_dbg(ql_dbg_async, vha, 0x5020,
  863. "FCF Configuration Error -- %04x %04x %04x.\n",
  864. mb[1], mb[2], mb[3]);
  865. break;
  866. case MBA_IDC_COMPLETE:
  867. case MBA_IDC_NOTIFY:
  868. case MBA_IDC_TIME_EXT:
  869. if (IS_QLA81XX(vha->hw))
  870. qla81xx_idc_event(vha, mb[0], mb[1]);
  871. break;
  872. case MBA_IDC_AEN:
  873. mb[4] = RD_REG_WORD(&reg24->mailbox4);
  874. mb[5] = RD_REG_WORD(&reg24->mailbox5);
  875. mb[6] = RD_REG_WORD(&reg24->mailbox6);
  876. mb[7] = RD_REG_WORD(&reg24->mailbox7);
  877. qla83xx_handle_8200_aen(vha, mb);
  878. break;
  879. default:
  880. ql_dbg(ql_dbg_async, vha, 0x5057,
  881. "Unknown AEN:%04x %04x %04x %04x\n",
  882. mb[0], mb[1], mb[2], mb[3]);
  883. }
  884. qlt_async_event(mb[0], vha, mb);
  885. if (!vha->vp_idx && ha->num_vhosts)
  886. qla2x00_alert_all_vps(rsp, mb);
  887. }
  888. /**
  889. * qla2x00_process_completed_request() - Process a Fast Post response.
  890. * @ha: SCSI driver HA context
  891. * @index: SRB index
  892. */
  893. static void
  894. qla2x00_process_completed_request(struct scsi_qla_host *vha,
  895. struct req_que *req, uint32_t index)
  896. {
  897. srb_t *sp;
  898. struct qla_hw_data *ha = vha->hw;
  899. /* Validate handle. */
  900. if (index >= MAX_OUTSTANDING_COMMANDS) {
  901. ql_log(ql_log_warn, vha, 0x3014,
  902. "Invalid SCSI command index (%x).\n", index);
  903. if (IS_QLA82XX(ha))
  904. set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
  905. else
  906. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  907. return;
  908. }
  909. sp = req->outstanding_cmds[index];
  910. if (sp) {
  911. /* Free outstanding command slot. */
  912. req->outstanding_cmds[index] = NULL;
  913. /* Save ISP completion status */
  914. sp->done(ha, sp, DID_OK << 16);
  915. } else {
  916. ql_log(ql_log_warn, vha, 0x3016, "Invalid SCSI SRB.\n");
  917. if (IS_QLA82XX(ha))
  918. set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
  919. else
  920. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  921. }
  922. }
  923. static srb_t *
  924. qla2x00_get_sp_from_handle(scsi_qla_host_t *vha, const char *func,
  925. struct req_que *req, void *iocb)
  926. {
  927. struct qla_hw_data *ha = vha->hw;
  928. sts_entry_t *pkt = iocb;
  929. srb_t *sp = NULL;
  930. uint16_t index;
  931. index = LSW(pkt->handle);
  932. if (index >= MAX_OUTSTANDING_COMMANDS) {
  933. ql_log(ql_log_warn, vha, 0x5031,
  934. "Invalid command index (%x).\n", index);
  935. if (IS_QLA82XX(ha))
  936. set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
  937. else
  938. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  939. goto done;
  940. }
  941. sp = req->outstanding_cmds[index];
  942. if (!sp) {
  943. ql_log(ql_log_warn, vha, 0x5032,
  944. "Invalid completion handle (%x) -- timed-out.\n", index);
  945. return sp;
  946. }
  947. if (sp->handle != index) {
  948. ql_log(ql_log_warn, vha, 0x5033,
  949. "SRB handle (%x) mismatch %x.\n", sp->handle, index);
  950. return NULL;
  951. }
  952. req->outstanding_cmds[index] = NULL;
  953. done:
  954. return sp;
  955. }
  956. static void
  957. qla2x00_mbx_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
  958. struct mbx_entry *mbx)
  959. {
  960. const char func[] = "MBX-IOCB";
  961. const char *type;
  962. fc_port_t *fcport;
  963. srb_t *sp;
  964. struct srb_iocb *lio;
  965. uint16_t *data;
  966. uint16_t status;
  967. sp = qla2x00_get_sp_from_handle(vha, func, req, mbx);
  968. if (!sp)
  969. return;
  970. lio = &sp->u.iocb_cmd;
  971. type = sp->name;
  972. fcport = sp->fcport;
  973. data = lio->u.logio.data;
  974. data[0] = MBS_COMMAND_ERROR;
  975. data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
  976. QLA_LOGIO_LOGIN_RETRIED : 0;
  977. if (mbx->entry_status) {
  978. ql_dbg(ql_dbg_async, vha, 0x5043,
  979. "Async-%s error entry - hdl=%x portid=%02x%02x%02x "
  980. "entry-status=%x status=%x state-flag=%x "
  981. "status-flags=%x.\n", type, sp->handle,
  982. fcport->d_id.b.domain, fcport->d_id.b.area,
  983. fcport->d_id.b.al_pa, mbx->entry_status,
  984. le16_to_cpu(mbx->status), le16_to_cpu(mbx->state_flags),
  985. le16_to_cpu(mbx->status_flags));
  986. ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x5029,
  987. (uint8_t *)mbx, sizeof(*mbx));
  988. goto logio_done;
  989. }
  990. status = le16_to_cpu(mbx->status);
  991. if (status == 0x30 && sp->type == SRB_LOGIN_CMD &&
  992. le16_to_cpu(mbx->mb0) == MBS_COMMAND_COMPLETE)
  993. status = 0;
  994. if (!status && le16_to_cpu(mbx->mb0) == MBS_COMMAND_COMPLETE) {
  995. ql_dbg(ql_dbg_async, vha, 0x5045,
  996. "Async-%s complete - hdl=%x portid=%02x%02x%02x mbx1=%x.\n",
  997. type, sp->handle, fcport->d_id.b.domain,
  998. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  999. le16_to_cpu(mbx->mb1));
  1000. data[0] = MBS_COMMAND_COMPLETE;
  1001. if (sp->type == SRB_LOGIN_CMD) {
  1002. fcport->port_type = FCT_TARGET;
  1003. if (le16_to_cpu(mbx->mb1) & BIT_0)
  1004. fcport->port_type = FCT_INITIATOR;
  1005. else if (le16_to_cpu(mbx->mb1) & BIT_1)
  1006. fcport->flags |= FCF_FCP2_DEVICE;
  1007. }
  1008. goto logio_done;
  1009. }
  1010. data[0] = le16_to_cpu(mbx->mb0);
  1011. switch (data[0]) {
  1012. case MBS_PORT_ID_USED:
  1013. data[1] = le16_to_cpu(mbx->mb1);
  1014. break;
  1015. case MBS_LOOP_ID_USED:
  1016. break;
  1017. default:
  1018. data[0] = MBS_COMMAND_ERROR;
  1019. break;
  1020. }
  1021. ql_log(ql_log_warn, vha, 0x5046,
  1022. "Async-%s failed - hdl=%x portid=%02x%02x%02x status=%x "
  1023. "mb0=%x mb1=%x mb2=%x mb6=%x mb7=%x.\n", type, sp->handle,
  1024. fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa,
  1025. status, le16_to_cpu(mbx->mb0), le16_to_cpu(mbx->mb1),
  1026. le16_to_cpu(mbx->mb2), le16_to_cpu(mbx->mb6),
  1027. le16_to_cpu(mbx->mb7));
  1028. logio_done:
  1029. sp->done(vha, sp, 0);
  1030. }
  1031. static void
  1032. qla2x00_ct_entry(scsi_qla_host_t *vha, struct req_que *req,
  1033. sts_entry_t *pkt, int iocb_type)
  1034. {
  1035. const char func[] = "CT_IOCB";
  1036. const char *type;
  1037. srb_t *sp;
  1038. struct fc_bsg_job *bsg_job;
  1039. uint16_t comp_status;
  1040. int res;
  1041. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  1042. if (!sp)
  1043. return;
  1044. bsg_job = sp->u.bsg_job;
  1045. type = "ct pass-through";
  1046. comp_status = le16_to_cpu(pkt->comp_status);
  1047. /* return FC_CTELS_STATUS_OK and leave the decoding of the ELS/CT
  1048. * fc payload to the caller
  1049. */
  1050. bsg_job->reply->reply_data.ctels_reply.status = FC_CTELS_STATUS_OK;
  1051. bsg_job->reply_len = sizeof(struct fc_bsg_reply);
  1052. if (comp_status != CS_COMPLETE) {
  1053. if (comp_status == CS_DATA_UNDERRUN) {
  1054. res = DID_OK << 16;
  1055. bsg_job->reply->reply_payload_rcv_len =
  1056. le16_to_cpu(((sts_entry_t *)pkt)->rsp_info_len);
  1057. ql_log(ql_log_warn, vha, 0x5048,
  1058. "CT pass-through-%s error "
  1059. "comp_status-status=0x%x total_byte = 0x%x.\n",
  1060. type, comp_status,
  1061. bsg_job->reply->reply_payload_rcv_len);
  1062. } else {
  1063. ql_log(ql_log_warn, vha, 0x5049,
  1064. "CT pass-through-%s error "
  1065. "comp_status-status=0x%x.\n", type, comp_status);
  1066. res = DID_ERROR << 16;
  1067. bsg_job->reply->reply_payload_rcv_len = 0;
  1068. }
  1069. ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x5035,
  1070. (uint8_t *)pkt, sizeof(*pkt));
  1071. } else {
  1072. res = DID_OK << 16;
  1073. bsg_job->reply->reply_payload_rcv_len =
  1074. bsg_job->reply_payload.payload_len;
  1075. bsg_job->reply_len = 0;
  1076. }
  1077. sp->done(vha, sp, res);
  1078. }
  1079. static void
  1080. qla24xx_els_ct_entry(scsi_qla_host_t *vha, struct req_que *req,
  1081. struct sts_entry_24xx *pkt, int iocb_type)
  1082. {
  1083. const char func[] = "ELS_CT_IOCB";
  1084. const char *type;
  1085. srb_t *sp;
  1086. struct fc_bsg_job *bsg_job;
  1087. uint16_t comp_status;
  1088. uint32_t fw_status[3];
  1089. uint8_t* fw_sts_ptr;
  1090. int res;
  1091. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  1092. if (!sp)
  1093. return;
  1094. bsg_job = sp->u.bsg_job;
  1095. type = NULL;
  1096. switch (sp->type) {
  1097. case SRB_ELS_CMD_RPT:
  1098. case SRB_ELS_CMD_HST:
  1099. type = "els";
  1100. break;
  1101. case SRB_CT_CMD:
  1102. type = "ct pass-through";
  1103. break;
  1104. default:
  1105. ql_dbg(ql_dbg_user, vha, 0x503e,
  1106. "Unrecognized SRB: (%p) type=%d.\n", sp, sp->type);
  1107. return;
  1108. }
  1109. comp_status = fw_status[0] = le16_to_cpu(pkt->comp_status);
  1110. fw_status[1] = le16_to_cpu(((struct els_sts_entry_24xx*)pkt)->error_subcode_1);
  1111. fw_status[2] = le16_to_cpu(((struct els_sts_entry_24xx*)pkt)->error_subcode_2);
  1112. /* return FC_CTELS_STATUS_OK and leave the decoding of the ELS/CT
  1113. * fc payload to the caller
  1114. */
  1115. bsg_job->reply->reply_data.ctels_reply.status = FC_CTELS_STATUS_OK;
  1116. bsg_job->reply_len = sizeof(struct fc_bsg_reply) + sizeof(fw_status);
  1117. if (comp_status != CS_COMPLETE) {
  1118. if (comp_status == CS_DATA_UNDERRUN) {
  1119. res = DID_OK << 16;
  1120. bsg_job->reply->reply_payload_rcv_len =
  1121. le16_to_cpu(((struct els_sts_entry_24xx *)pkt)->total_byte_count);
  1122. ql_dbg(ql_dbg_user, vha, 0x503f,
  1123. "ELS-CT pass-through-%s error hdl=%x comp_status-status=0x%x "
  1124. "error subcode 1=0x%x error subcode 2=0x%x total_byte = 0x%x.\n",
  1125. type, sp->handle, comp_status, fw_status[1], fw_status[2],
  1126. le16_to_cpu(((struct els_sts_entry_24xx *)
  1127. pkt)->total_byte_count));
  1128. fw_sts_ptr = ((uint8_t*)bsg_job->req->sense) + sizeof(struct fc_bsg_reply);
  1129. memcpy( fw_sts_ptr, fw_status, sizeof(fw_status));
  1130. }
  1131. else {
  1132. ql_dbg(ql_dbg_user, vha, 0x5040,
  1133. "ELS-CT pass-through-%s error hdl=%x comp_status-status=0x%x "
  1134. "error subcode 1=0x%x error subcode 2=0x%x.\n",
  1135. type, sp->handle, comp_status,
  1136. le16_to_cpu(((struct els_sts_entry_24xx *)
  1137. pkt)->error_subcode_1),
  1138. le16_to_cpu(((struct els_sts_entry_24xx *)
  1139. pkt)->error_subcode_2));
  1140. res = DID_ERROR << 16;
  1141. bsg_job->reply->reply_payload_rcv_len = 0;
  1142. fw_sts_ptr = ((uint8_t*)bsg_job->req->sense) + sizeof(struct fc_bsg_reply);
  1143. memcpy( fw_sts_ptr, fw_status, sizeof(fw_status));
  1144. }
  1145. ql_dump_buffer(ql_dbg_user + ql_dbg_buffer, vha, 0x5056,
  1146. (uint8_t *)pkt, sizeof(*pkt));
  1147. }
  1148. else {
  1149. res = DID_OK << 16;
  1150. bsg_job->reply->reply_payload_rcv_len = bsg_job->reply_payload.payload_len;
  1151. bsg_job->reply_len = 0;
  1152. }
  1153. sp->done(vha, sp, res);
  1154. }
  1155. static void
  1156. qla24xx_logio_entry(scsi_qla_host_t *vha, struct req_que *req,
  1157. struct logio_entry_24xx *logio)
  1158. {
  1159. const char func[] = "LOGIO-IOCB";
  1160. const char *type;
  1161. fc_port_t *fcport;
  1162. srb_t *sp;
  1163. struct srb_iocb *lio;
  1164. uint16_t *data;
  1165. uint32_t iop[2];
  1166. sp = qla2x00_get_sp_from_handle(vha, func, req, logio);
  1167. if (!sp)
  1168. return;
  1169. lio = &sp->u.iocb_cmd;
  1170. type = sp->name;
  1171. fcport = sp->fcport;
  1172. data = lio->u.logio.data;
  1173. data[0] = MBS_COMMAND_ERROR;
  1174. data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
  1175. QLA_LOGIO_LOGIN_RETRIED : 0;
  1176. if (logio->entry_status) {
  1177. ql_log(ql_log_warn, fcport->vha, 0x5034,
  1178. "Async-%s error entry - hdl=%x"
  1179. "portid=%02x%02x%02x entry-status=%x.\n",
  1180. type, sp->handle, fcport->d_id.b.domain,
  1181. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  1182. logio->entry_status);
  1183. ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x504d,
  1184. (uint8_t *)logio, sizeof(*logio));
  1185. goto logio_done;
  1186. }
  1187. if (le16_to_cpu(logio->comp_status) == CS_COMPLETE) {
  1188. ql_dbg(ql_dbg_async, fcport->vha, 0x5036,
  1189. "Async-%s complete - hdl=%x portid=%02x%02x%02x "
  1190. "iop0=%x.\n", type, sp->handle, fcport->d_id.b.domain,
  1191. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  1192. le32_to_cpu(logio->io_parameter[0]));
  1193. data[0] = MBS_COMMAND_COMPLETE;
  1194. if (sp->type != SRB_LOGIN_CMD)
  1195. goto logio_done;
  1196. iop[0] = le32_to_cpu(logio->io_parameter[0]);
  1197. if (iop[0] & BIT_4) {
  1198. fcport->port_type = FCT_TARGET;
  1199. if (iop[0] & BIT_8)
  1200. fcport->flags |= FCF_FCP2_DEVICE;
  1201. } else if (iop[0] & BIT_5)
  1202. fcport->port_type = FCT_INITIATOR;
  1203. if (iop[0] & BIT_7)
  1204. fcport->flags |= FCF_CONF_COMP_SUPPORTED;
  1205. if (logio->io_parameter[7] || logio->io_parameter[8])
  1206. fcport->supported_classes |= FC_COS_CLASS2;
  1207. if (logio->io_parameter[9] || logio->io_parameter[10])
  1208. fcport->supported_classes |= FC_COS_CLASS3;
  1209. goto logio_done;
  1210. }
  1211. iop[0] = le32_to_cpu(logio->io_parameter[0]);
  1212. iop[1] = le32_to_cpu(logio->io_parameter[1]);
  1213. switch (iop[0]) {
  1214. case LSC_SCODE_PORTID_USED:
  1215. data[0] = MBS_PORT_ID_USED;
  1216. data[1] = LSW(iop[1]);
  1217. break;
  1218. case LSC_SCODE_NPORT_USED:
  1219. data[0] = MBS_LOOP_ID_USED;
  1220. break;
  1221. default:
  1222. data[0] = MBS_COMMAND_ERROR;
  1223. break;
  1224. }
  1225. ql_dbg(ql_dbg_async, fcport->vha, 0x5037,
  1226. "Async-%s failed - hdl=%x portid=%02x%02x%02x comp=%x "
  1227. "iop0=%x iop1=%x.\n", type, sp->handle, fcport->d_id.b.domain,
  1228. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  1229. le16_to_cpu(logio->comp_status),
  1230. le32_to_cpu(logio->io_parameter[0]),
  1231. le32_to_cpu(logio->io_parameter[1]));
  1232. logio_done:
  1233. sp->done(vha, sp, 0);
  1234. }
  1235. static void
  1236. qla24xx_tm_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
  1237. struct tsk_mgmt_entry *tsk)
  1238. {
  1239. const char func[] = "TMF-IOCB";
  1240. const char *type;
  1241. fc_port_t *fcport;
  1242. srb_t *sp;
  1243. struct srb_iocb *iocb;
  1244. struct sts_entry_24xx *sts = (struct sts_entry_24xx *)tsk;
  1245. int error = 1;
  1246. sp = qla2x00_get_sp_from_handle(vha, func, req, tsk);
  1247. if (!sp)
  1248. return;
  1249. iocb = &sp->u.iocb_cmd;
  1250. type = sp->name;
  1251. fcport = sp->fcport;
  1252. if (sts->entry_status) {
  1253. ql_log(ql_log_warn, fcport->vha, 0x5038,
  1254. "Async-%s error - hdl=%x entry-status(%x).\n",
  1255. type, sp->handle, sts->entry_status);
  1256. } else if (sts->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) {
  1257. ql_log(ql_log_warn, fcport->vha, 0x5039,
  1258. "Async-%s error - hdl=%x completion status(%x).\n",
  1259. type, sp->handle, sts->comp_status);
  1260. } else if (!(le16_to_cpu(sts->scsi_status) &
  1261. SS_RESPONSE_INFO_LEN_VALID)) {
  1262. ql_log(ql_log_warn, fcport->vha, 0x503a,
  1263. "Async-%s error - hdl=%x no response info(%x).\n",
  1264. type, sp->handle, sts->scsi_status);
  1265. } else if (le32_to_cpu(sts->rsp_data_len) < 4) {
  1266. ql_log(ql_log_warn, fcport->vha, 0x503b,
  1267. "Async-%s error - hdl=%x not enough response(%d).\n",
  1268. type, sp->handle, sts->rsp_data_len);
  1269. } else if (sts->data[3]) {
  1270. ql_log(ql_log_warn, fcport->vha, 0x503c,
  1271. "Async-%s error - hdl=%x response(%x).\n",
  1272. type, sp->handle, sts->data[3]);
  1273. } else {
  1274. error = 0;
  1275. }
  1276. if (error) {
  1277. iocb->u.tmf.data = error;
  1278. ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x5055,
  1279. (uint8_t *)sts, sizeof(*sts));
  1280. }
  1281. sp->done(vha, sp, 0);
  1282. }
  1283. /**
  1284. * qla2x00_process_response_queue() - Process response queue entries.
  1285. * @ha: SCSI driver HA context
  1286. */
  1287. void
  1288. qla2x00_process_response_queue(struct rsp_que *rsp)
  1289. {
  1290. struct scsi_qla_host *vha;
  1291. struct qla_hw_data *ha = rsp->hw;
  1292. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  1293. sts_entry_t *pkt;
  1294. uint16_t handle_cnt;
  1295. uint16_t cnt;
  1296. vha = pci_get_drvdata(ha->pdev);
  1297. if (!vha->flags.online)
  1298. return;
  1299. while (rsp->ring_ptr->signature != RESPONSE_PROCESSED) {
  1300. pkt = (sts_entry_t *)rsp->ring_ptr;
  1301. rsp->ring_index++;
  1302. if (rsp->ring_index == rsp->length) {
  1303. rsp->ring_index = 0;
  1304. rsp->ring_ptr = rsp->ring;
  1305. } else {
  1306. rsp->ring_ptr++;
  1307. }
  1308. if (pkt->entry_status != 0) {
  1309. qla2x00_error_entry(vha, rsp, pkt);
  1310. ((response_t *)pkt)->signature = RESPONSE_PROCESSED;
  1311. wmb();
  1312. continue;
  1313. }
  1314. switch (pkt->entry_type) {
  1315. case STATUS_TYPE:
  1316. qla2x00_status_entry(vha, rsp, pkt);
  1317. break;
  1318. case STATUS_TYPE_21:
  1319. handle_cnt = ((sts21_entry_t *)pkt)->handle_count;
  1320. for (cnt = 0; cnt < handle_cnt; cnt++) {
  1321. qla2x00_process_completed_request(vha, rsp->req,
  1322. ((sts21_entry_t *)pkt)->handle[cnt]);
  1323. }
  1324. break;
  1325. case STATUS_TYPE_22:
  1326. handle_cnt = ((sts22_entry_t *)pkt)->handle_count;
  1327. for (cnt = 0; cnt < handle_cnt; cnt++) {
  1328. qla2x00_process_completed_request(vha, rsp->req,
  1329. ((sts22_entry_t *)pkt)->handle[cnt]);
  1330. }
  1331. break;
  1332. case STATUS_CONT_TYPE:
  1333. qla2x00_status_cont_entry(rsp, (sts_cont_entry_t *)pkt);
  1334. break;
  1335. case MBX_IOCB_TYPE:
  1336. qla2x00_mbx_iocb_entry(vha, rsp->req,
  1337. (struct mbx_entry *)pkt);
  1338. break;
  1339. case CT_IOCB_TYPE:
  1340. qla2x00_ct_entry(vha, rsp->req, pkt, CT_IOCB_TYPE);
  1341. break;
  1342. default:
  1343. /* Type Not Supported. */
  1344. ql_log(ql_log_warn, vha, 0x504a,
  1345. "Received unknown response pkt type %x "
  1346. "entry status=%x.\n",
  1347. pkt->entry_type, pkt->entry_status);
  1348. break;
  1349. }
  1350. ((response_t *)pkt)->signature = RESPONSE_PROCESSED;
  1351. wmb();
  1352. }
  1353. /* Adjust ring index */
  1354. WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), rsp->ring_index);
  1355. }
  1356. static inline void
  1357. qla2x00_handle_sense(srb_t *sp, uint8_t *sense_data, uint32_t par_sense_len,
  1358. uint32_t sense_len, struct rsp_que *rsp, int res)
  1359. {
  1360. struct scsi_qla_host *vha = sp->fcport->vha;
  1361. struct scsi_cmnd *cp = GET_CMD_SP(sp);
  1362. uint32_t track_sense_len;
  1363. if (sense_len >= SCSI_SENSE_BUFFERSIZE)
  1364. sense_len = SCSI_SENSE_BUFFERSIZE;
  1365. SET_CMD_SENSE_LEN(sp, sense_len);
  1366. SET_CMD_SENSE_PTR(sp, cp->sense_buffer);
  1367. track_sense_len = sense_len;
  1368. if (sense_len > par_sense_len)
  1369. sense_len = par_sense_len;
  1370. memcpy(cp->sense_buffer, sense_data, sense_len);
  1371. SET_CMD_SENSE_PTR(sp, cp->sense_buffer + sense_len);
  1372. track_sense_len -= sense_len;
  1373. SET_CMD_SENSE_LEN(sp, track_sense_len);
  1374. if (track_sense_len != 0) {
  1375. rsp->status_srb = sp;
  1376. cp->result = res;
  1377. }
  1378. if (sense_len) {
  1379. ql_dbg(ql_dbg_io + ql_dbg_buffer, vha, 0x301c,
  1380. "Check condition Sense data, nexus%ld:%d:%d cmd=%p.\n",
  1381. sp->fcport->vha->host_no, cp->device->id, cp->device->lun,
  1382. cp);
  1383. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x302b,
  1384. cp->sense_buffer, sense_len);
  1385. }
  1386. }
  1387. struct scsi_dif_tuple {
  1388. __be16 guard; /* Checksum */
  1389. __be16 app_tag; /* APPL identifier */
  1390. __be32 ref_tag; /* Target LBA or indirect LBA */
  1391. };
  1392. /*
  1393. * Checks the guard or meta-data for the type of error
  1394. * detected by the HBA. In case of errors, we set the
  1395. * ASC/ASCQ fields in the sense buffer with ILLEGAL_REQUEST
  1396. * to indicate to the kernel that the HBA detected error.
  1397. */
  1398. static inline int
  1399. qla2x00_handle_dif_error(srb_t *sp, struct sts_entry_24xx *sts24)
  1400. {
  1401. struct scsi_qla_host *vha = sp->fcport->vha;
  1402. struct scsi_cmnd *cmd = GET_CMD_SP(sp);
  1403. uint8_t *ap = &sts24->data[12];
  1404. uint8_t *ep = &sts24->data[20];
  1405. uint32_t e_ref_tag, a_ref_tag;
  1406. uint16_t e_app_tag, a_app_tag;
  1407. uint16_t e_guard, a_guard;
  1408. /*
  1409. * swab32 of the "data" field in the beginning of qla2x00_status_entry()
  1410. * would make guard field appear at offset 2
  1411. */
  1412. a_guard = le16_to_cpu(*(uint16_t *)(ap + 2));
  1413. a_app_tag = le16_to_cpu(*(uint16_t *)(ap + 0));
  1414. a_ref_tag = le32_to_cpu(*(uint32_t *)(ap + 4));
  1415. e_guard = le16_to_cpu(*(uint16_t *)(ep + 2));
  1416. e_app_tag = le16_to_cpu(*(uint16_t *)(ep + 0));
  1417. e_ref_tag = le32_to_cpu(*(uint32_t *)(ep + 4));
  1418. ql_dbg(ql_dbg_io, vha, 0x3023,
  1419. "iocb(s) %p Returned STATUS.\n", sts24);
  1420. ql_dbg(ql_dbg_io, vha, 0x3024,
  1421. "DIF ERROR in cmd 0x%x lba 0x%llx act ref"
  1422. " tag=0x%x, exp ref_tag=0x%x, act app tag=0x%x, exp app"
  1423. " tag=0x%x, act guard=0x%x, exp guard=0x%x.\n",
  1424. cmd->cmnd[0], (u64)scsi_get_lba(cmd), a_ref_tag, e_ref_tag,
  1425. a_app_tag, e_app_tag, a_guard, e_guard);
  1426. /*
  1427. * Ignore sector if:
  1428. * For type 3: ref & app tag is all 'f's
  1429. * For type 0,1,2: app tag is all 'f's
  1430. */
  1431. if ((a_app_tag == 0xffff) &&
  1432. ((scsi_get_prot_type(cmd) != SCSI_PROT_DIF_TYPE3) ||
  1433. (a_ref_tag == 0xffffffff))) {
  1434. uint32_t blocks_done, resid;
  1435. sector_t lba_s = scsi_get_lba(cmd);
  1436. /* 2TB boundary case covered automatically with this */
  1437. blocks_done = e_ref_tag - (uint32_t)lba_s + 1;
  1438. resid = scsi_bufflen(cmd) - (blocks_done *
  1439. cmd->device->sector_size);
  1440. scsi_set_resid(cmd, resid);
  1441. cmd->result = DID_OK << 16;
  1442. /* Update protection tag */
  1443. if (scsi_prot_sg_count(cmd)) {
  1444. uint32_t i, j = 0, k = 0, num_ent;
  1445. struct scatterlist *sg;
  1446. struct sd_dif_tuple *spt;
  1447. /* Patch the corresponding protection tags */
  1448. scsi_for_each_prot_sg(cmd, sg,
  1449. scsi_prot_sg_count(cmd), i) {
  1450. num_ent = sg_dma_len(sg) / 8;
  1451. if (k + num_ent < blocks_done) {
  1452. k += num_ent;
  1453. continue;
  1454. }
  1455. j = blocks_done - k - 1;
  1456. k = blocks_done;
  1457. break;
  1458. }
  1459. if (k != blocks_done) {
  1460. ql_log(ql_log_warn, vha, 0x302f,
  1461. "unexpected tag values tag:lba=%x:%llx)\n",
  1462. e_ref_tag, (unsigned long long)lba_s);
  1463. return 1;
  1464. }
  1465. spt = page_address(sg_page(sg)) + sg->offset;
  1466. spt += j;
  1467. spt->app_tag = 0xffff;
  1468. if (scsi_get_prot_type(cmd) == SCSI_PROT_DIF_TYPE3)
  1469. spt->ref_tag = 0xffffffff;
  1470. }
  1471. return 0;
  1472. }
  1473. /* check guard */
  1474. if (e_guard != a_guard) {
  1475. scsi_build_sense_buffer(1, cmd->sense_buffer, ILLEGAL_REQUEST,
  1476. 0x10, 0x1);
  1477. set_driver_byte(cmd, DRIVER_SENSE);
  1478. set_host_byte(cmd, DID_ABORT);
  1479. cmd->result |= SAM_STAT_CHECK_CONDITION << 1;
  1480. return 1;
  1481. }
  1482. /* check ref tag */
  1483. if (e_ref_tag != a_ref_tag) {
  1484. scsi_build_sense_buffer(1, cmd->sense_buffer, ILLEGAL_REQUEST,
  1485. 0x10, 0x3);
  1486. set_driver_byte(cmd, DRIVER_SENSE);
  1487. set_host_byte(cmd, DID_ABORT);
  1488. cmd->result |= SAM_STAT_CHECK_CONDITION << 1;
  1489. return 1;
  1490. }
  1491. /* check appl tag */
  1492. if (e_app_tag != a_app_tag) {
  1493. scsi_build_sense_buffer(1, cmd->sense_buffer, ILLEGAL_REQUEST,
  1494. 0x10, 0x2);
  1495. set_driver_byte(cmd, DRIVER_SENSE);
  1496. set_host_byte(cmd, DID_ABORT);
  1497. cmd->result |= SAM_STAT_CHECK_CONDITION << 1;
  1498. return 1;
  1499. }
  1500. return 1;
  1501. }
  1502. static void
  1503. qla25xx_process_bidir_status_iocb(scsi_qla_host_t *vha, void *pkt,
  1504. struct req_que *req, uint32_t index)
  1505. {
  1506. struct qla_hw_data *ha = vha->hw;
  1507. srb_t *sp;
  1508. uint16_t comp_status;
  1509. uint16_t scsi_status;
  1510. uint16_t thread_id;
  1511. uint32_t rval = EXT_STATUS_OK;
  1512. struct fc_bsg_job *bsg_job = NULL;
  1513. sts_entry_t *sts;
  1514. struct sts_entry_24xx *sts24;
  1515. sts = (sts_entry_t *) pkt;
  1516. sts24 = (struct sts_entry_24xx *) pkt;
  1517. /* Validate handle. */
  1518. if (index >= MAX_OUTSTANDING_COMMANDS) {
  1519. ql_log(ql_log_warn, vha, 0x70af,
  1520. "Invalid SCSI completion handle 0x%x.\n", index);
  1521. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1522. return;
  1523. }
  1524. sp = req->outstanding_cmds[index];
  1525. if (sp) {
  1526. /* Free outstanding command slot. */
  1527. req->outstanding_cmds[index] = NULL;
  1528. bsg_job = sp->u.bsg_job;
  1529. } else {
  1530. ql_log(ql_log_warn, vha, 0x70b0,
  1531. "Req:%d: Invalid ISP SCSI completion handle(0x%x)\n",
  1532. req->id, index);
  1533. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1534. return;
  1535. }
  1536. if (IS_FWI2_CAPABLE(ha)) {
  1537. comp_status = le16_to_cpu(sts24->comp_status);
  1538. scsi_status = le16_to_cpu(sts24->scsi_status) & SS_MASK;
  1539. } else {
  1540. comp_status = le16_to_cpu(sts->comp_status);
  1541. scsi_status = le16_to_cpu(sts->scsi_status) & SS_MASK;
  1542. }
  1543. thread_id = bsg_job->request->rqst_data.h_vendor.vendor_cmd[1];
  1544. switch (comp_status) {
  1545. case CS_COMPLETE:
  1546. if (scsi_status == 0) {
  1547. bsg_job->reply->reply_payload_rcv_len =
  1548. bsg_job->reply_payload.payload_len;
  1549. rval = EXT_STATUS_OK;
  1550. }
  1551. goto done;
  1552. case CS_DATA_OVERRUN:
  1553. ql_dbg(ql_dbg_user, vha, 0x70b1,
  1554. "Command completed with date overrun thread_id=%d\n",
  1555. thread_id);
  1556. rval = EXT_STATUS_DATA_OVERRUN;
  1557. break;
  1558. case CS_DATA_UNDERRUN:
  1559. ql_dbg(ql_dbg_user, vha, 0x70b2,
  1560. "Command completed with date underrun thread_id=%d\n",
  1561. thread_id);
  1562. rval = EXT_STATUS_DATA_UNDERRUN;
  1563. break;
  1564. case CS_BIDIR_RD_OVERRUN:
  1565. ql_dbg(ql_dbg_user, vha, 0x70b3,
  1566. "Command completed with read data overrun thread_id=%d\n",
  1567. thread_id);
  1568. rval = EXT_STATUS_DATA_OVERRUN;
  1569. break;
  1570. case CS_BIDIR_RD_WR_OVERRUN:
  1571. ql_dbg(ql_dbg_user, vha, 0x70b4,
  1572. "Command completed with read and write data overrun "
  1573. "thread_id=%d\n", thread_id);
  1574. rval = EXT_STATUS_DATA_OVERRUN;
  1575. break;
  1576. case CS_BIDIR_RD_OVERRUN_WR_UNDERRUN:
  1577. ql_dbg(ql_dbg_user, vha, 0x70b5,
  1578. "Command completed with read data over and write data "
  1579. "underrun thread_id=%d\n", thread_id);
  1580. rval = EXT_STATUS_DATA_OVERRUN;
  1581. break;
  1582. case CS_BIDIR_RD_UNDERRUN:
  1583. ql_dbg(ql_dbg_user, vha, 0x70b6,
  1584. "Command completed with read data data underrun "
  1585. "thread_id=%d\n", thread_id);
  1586. rval = EXT_STATUS_DATA_UNDERRUN;
  1587. break;
  1588. case CS_BIDIR_RD_UNDERRUN_WR_OVERRUN:
  1589. ql_dbg(ql_dbg_user, vha, 0x70b7,
  1590. "Command completed with read data under and write data "
  1591. "overrun thread_id=%d\n", thread_id);
  1592. rval = EXT_STATUS_DATA_UNDERRUN;
  1593. break;
  1594. case CS_BIDIR_RD_WR_UNDERRUN:
  1595. ql_dbg(ql_dbg_user, vha, 0x70b8,
  1596. "Command completed with read and write data underrun "
  1597. "thread_id=%d\n", thread_id);
  1598. rval = EXT_STATUS_DATA_UNDERRUN;
  1599. break;
  1600. case CS_BIDIR_DMA:
  1601. ql_dbg(ql_dbg_user, vha, 0x70b9,
  1602. "Command completed with data DMA error thread_id=%d\n",
  1603. thread_id);
  1604. rval = EXT_STATUS_DMA_ERR;
  1605. break;
  1606. case CS_TIMEOUT:
  1607. ql_dbg(ql_dbg_user, vha, 0x70ba,
  1608. "Command completed with timeout thread_id=%d\n",
  1609. thread_id);
  1610. rval = EXT_STATUS_TIMEOUT;
  1611. break;
  1612. default:
  1613. ql_dbg(ql_dbg_user, vha, 0x70bb,
  1614. "Command completed with completion status=0x%x "
  1615. "thread_id=%d\n", comp_status, thread_id);
  1616. rval = EXT_STATUS_ERR;
  1617. break;
  1618. }
  1619. bsg_job->reply->reply_payload_rcv_len = 0;
  1620. done:
  1621. /* Return the vendor specific reply to API */
  1622. bsg_job->reply->reply_data.vendor_reply.vendor_rsp[0] = rval;
  1623. bsg_job->reply_len = sizeof(struct fc_bsg_reply);
  1624. /* Always return DID_OK, bsg will send the vendor specific response
  1625. * in this case only */
  1626. sp->done(vha, sp, (DID_OK << 6));
  1627. }
  1628. /**
  1629. * qla2x00_status_entry() - Process a Status IOCB entry.
  1630. * @ha: SCSI driver HA context
  1631. * @pkt: Entry pointer
  1632. */
  1633. static void
  1634. qla2x00_status_entry(scsi_qla_host_t *vha, struct rsp_que *rsp, void *pkt)
  1635. {
  1636. srb_t *sp;
  1637. fc_port_t *fcport;
  1638. struct scsi_cmnd *cp;
  1639. sts_entry_t *sts;
  1640. struct sts_entry_24xx *sts24;
  1641. uint16_t comp_status;
  1642. uint16_t scsi_status;
  1643. uint16_t ox_id;
  1644. uint8_t lscsi_status;
  1645. int32_t resid;
  1646. uint32_t sense_len, par_sense_len, rsp_info_len, resid_len,
  1647. fw_resid_len;
  1648. uint8_t *rsp_info, *sense_data;
  1649. struct qla_hw_data *ha = vha->hw;
  1650. uint32_t handle;
  1651. uint16_t que;
  1652. struct req_que *req;
  1653. int logit = 1;
  1654. int res = 0;
  1655. uint16_t state_flags = 0;
  1656. sts = (sts_entry_t *) pkt;
  1657. sts24 = (struct sts_entry_24xx *) pkt;
  1658. if (IS_FWI2_CAPABLE(ha)) {
  1659. comp_status = le16_to_cpu(sts24->comp_status);
  1660. scsi_status = le16_to_cpu(sts24->scsi_status) & SS_MASK;
  1661. state_flags = le16_to_cpu(sts24->state_flags);
  1662. } else {
  1663. comp_status = le16_to_cpu(sts->comp_status);
  1664. scsi_status = le16_to_cpu(sts->scsi_status) & SS_MASK;
  1665. }
  1666. handle = (uint32_t) LSW(sts->handle);
  1667. que = MSW(sts->handle);
  1668. req = ha->req_q_map[que];
  1669. /* Validate handle. */
  1670. if (handle < MAX_OUTSTANDING_COMMANDS) {
  1671. sp = req->outstanding_cmds[handle];
  1672. } else
  1673. sp = NULL;
  1674. if (sp == NULL) {
  1675. ql_dbg(ql_dbg_io, vha, 0x3017,
  1676. "Invalid status handle (0x%x).\n", sts->handle);
  1677. if (IS_QLA82XX(ha))
  1678. set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
  1679. else
  1680. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1681. qla2xxx_wake_dpc(vha);
  1682. return;
  1683. }
  1684. if (unlikely((state_flags & BIT_1) && (sp->type == SRB_BIDI_CMD))) {
  1685. qla25xx_process_bidir_status_iocb(vha, pkt, req, handle);
  1686. return;
  1687. }
  1688. /* Fast path completion. */
  1689. if (comp_status == CS_COMPLETE && scsi_status == 0) {
  1690. qla2x00_process_completed_request(vha, req, handle);
  1691. return;
  1692. }
  1693. req->outstanding_cmds[handle] = NULL;
  1694. cp = GET_CMD_SP(sp);
  1695. if (cp == NULL) {
  1696. ql_dbg(ql_dbg_io, vha, 0x3018,
  1697. "Command already returned (0x%x/%p).\n",
  1698. sts->handle, sp);
  1699. return;
  1700. }
  1701. lscsi_status = scsi_status & STATUS_MASK;
  1702. fcport = sp->fcport;
  1703. ox_id = 0;
  1704. sense_len = par_sense_len = rsp_info_len = resid_len =
  1705. fw_resid_len = 0;
  1706. if (IS_FWI2_CAPABLE(ha)) {
  1707. if (scsi_status & SS_SENSE_LEN_VALID)
  1708. sense_len = le32_to_cpu(sts24->sense_len);
  1709. if (scsi_status & SS_RESPONSE_INFO_LEN_VALID)
  1710. rsp_info_len = le32_to_cpu(sts24->rsp_data_len);
  1711. if (scsi_status & (SS_RESIDUAL_UNDER | SS_RESIDUAL_OVER))
  1712. resid_len = le32_to_cpu(sts24->rsp_residual_count);
  1713. if (comp_status == CS_DATA_UNDERRUN)
  1714. fw_resid_len = le32_to_cpu(sts24->residual_len);
  1715. rsp_info = sts24->data;
  1716. sense_data = sts24->data;
  1717. host_to_fcp_swap(sts24->data, sizeof(sts24->data));
  1718. ox_id = le16_to_cpu(sts24->ox_id);
  1719. par_sense_len = sizeof(sts24->data);
  1720. } else {
  1721. if (scsi_status & SS_SENSE_LEN_VALID)
  1722. sense_len = le16_to_cpu(sts->req_sense_length);
  1723. if (scsi_status & SS_RESPONSE_INFO_LEN_VALID)
  1724. rsp_info_len = le16_to_cpu(sts->rsp_info_len);
  1725. resid_len = le32_to_cpu(sts->residual_length);
  1726. rsp_info = sts->rsp_info;
  1727. sense_data = sts->req_sense_data;
  1728. par_sense_len = sizeof(sts->req_sense_data);
  1729. }
  1730. /* Check for any FCP transport errors. */
  1731. if (scsi_status & SS_RESPONSE_INFO_LEN_VALID) {
  1732. /* Sense data lies beyond any FCP RESPONSE data. */
  1733. if (IS_FWI2_CAPABLE(ha)) {
  1734. sense_data += rsp_info_len;
  1735. par_sense_len -= rsp_info_len;
  1736. }
  1737. if (rsp_info_len > 3 && rsp_info[3]) {
  1738. ql_dbg(ql_dbg_io, fcport->vha, 0x3019,
  1739. "FCP I/O protocol failure (0x%x/0x%x).\n",
  1740. rsp_info_len, rsp_info[3]);
  1741. res = DID_BUS_BUSY << 16;
  1742. goto out;
  1743. }
  1744. }
  1745. /* Check for overrun. */
  1746. if (IS_FWI2_CAPABLE(ha) && comp_status == CS_COMPLETE &&
  1747. scsi_status & SS_RESIDUAL_OVER)
  1748. comp_status = CS_DATA_OVERRUN;
  1749. /*
  1750. * Based on Host and scsi status generate status code for Linux
  1751. */
  1752. switch (comp_status) {
  1753. case CS_COMPLETE:
  1754. case CS_QUEUE_FULL:
  1755. if (scsi_status == 0) {
  1756. res = DID_OK << 16;
  1757. break;
  1758. }
  1759. if (scsi_status & (SS_RESIDUAL_UNDER | SS_RESIDUAL_OVER)) {
  1760. resid = resid_len;
  1761. scsi_set_resid(cp, resid);
  1762. if (!lscsi_status &&
  1763. ((unsigned)(scsi_bufflen(cp) - resid) <
  1764. cp->underflow)) {
  1765. ql_dbg(ql_dbg_io, fcport->vha, 0x301a,
  1766. "Mid-layer underflow "
  1767. "detected (0x%x of 0x%x bytes).\n",
  1768. resid, scsi_bufflen(cp));
  1769. res = DID_ERROR << 16;
  1770. break;
  1771. }
  1772. }
  1773. res = DID_OK << 16 | lscsi_status;
  1774. if (lscsi_status == SAM_STAT_TASK_SET_FULL) {
  1775. ql_dbg(ql_dbg_io, fcport->vha, 0x301b,
  1776. "QUEUE FULL detected.\n");
  1777. break;
  1778. }
  1779. logit = 0;
  1780. if (lscsi_status != SS_CHECK_CONDITION)
  1781. break;
  1782. memset(cp->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
  1783. if (!(scsi_status & SS_SENSE_LEN_VALID))
  1784. break;
  1785. qla2x00_handle_sense(sp, sense_data, par_sense_len, sense_len,
  1786. rsp, res);
  1787. break;
  1788. case CS_DATA_UNDERRUN:
  1789. /* Use F/W calculated residual length. */
  1790. resid = IS_FWI2_CAPABLE(ha) ? fw_resid_len : resid_len;
  1791. scsi_set_resid(cp, resid);
  1792. if (scsi_status & SS_RESIDUAL_UNDER) {
  1793. if (IS_FWI2_CAPABLE(ha) && fw_resid_len != resid_len) {
  1794. ql_dbg(ql_dbg_io, fcport->vha, 0x301d,
  1795. "Dropped frame(s) detected "
  1796. "(0x%x of 0x%x bytes).\n",
  1797. resid, scsi_bufflen(cp));
  1798. res = DID_ERROR << 16 | lscsi_status;
  1799. goto check_scsi_status;
  1800. }
  1801. if (!lscsi_status &&
  1802. ((unsigned)(scsi_bufflen(cp) - resid) <
  1803. cp->underflow)) {
  1804. ql_dbg(ql_dbg_io, fcport->vha, 0x301e,
  1805. "Mid-layer underflow "
  1806. "detected (0x%x of 0x%x bytes).\n",
  1807. resid, scsi_bufflen(cp));
  1808. res = DID_ERROR << 16;
  1809. break;
  1810. }
  1811. } else if (lscsi_status != SAM_STAT_TASK_SET_FULL &&
  1812. lscsi_status != SAM_STAT_BUSY) {
  1813. /*
  1814. * scsi status of task set and busy are considered to be
  1815. * task not completed.
  1816. */
  1817. ql_dbg(ql_dbg_io, fcport->vha, 0x301f,
  1818. "Dropped frame(s) detected (0x%x "
  1819. "of 0x%x bytes).\n", resid,
  1820. scsi_bufflen(cp));
  1821. res = DID_ERROR << 16 | lscsi_status;
  1822. goto check_scsi_status;
  1823. } else {
  1824. ql_dbg(ql_dbg_io, fcport->vha, 0x3030,
  1825. "scsi_status: 0x%x, lscsi_status: 0x%x\n",
  1826. scsi_status, lscsi_status);
  1827. }
  1828. res = DID_OK << 16 | lscsi_status;
  1829. logit = 0;
  1830. check_scsi_status:
  1831. /*
  1832. * Check to see if SCSI Status is non zero. If so report SCSI
  1833. * Status.
  1834. */
  1835. if (lscsi_status != 0) {
  1836. if (lscsi_status == SAM_STAT_TASK_SET_FULL) {
  1837. ql_dbg(ql_dbg_io, fcport->vha, 0x3020,
  1838. "QUEUE FULL detected.\n");
  1839. logit = 1;
  1840. break;
  1841. }
  1842. if (lscsi_status != SS_CHECK_CONDITION)
  1843. break;
  1844. memset(cp->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
  1845. if (!(scsi_status & SS_SENSE_LEN_VALID))
  1846. break;
  1847. qla2x00_handle_sense(sp, sense_data, par_sense_len,
  1848. sense_len, rsp, res);
  1849. }
  1850. break;
  1851. case CS_PORT_LOGGED_OUT:
  1852. case CS_PORT_CONFIG_CHG:
  1853. case CS_PORT_BUSY:
  1854. case CS_INCOMPLETE:
  1855. case CS_PORT_UNAVAILABLE:
  1856. case CS_TIMEOUT:
  1857. case CS_RESET:
  1858. /*
  1859. * We are going to have the fc class block the rport
  1860. * while we try to recover so instruct the mid layer
  1861. * to requeue until the class decides how to handle this.
  1862. */
  1863. res = DID_TRANSPORT_DISRUPTED << 16;
  1864. if (comp_status == CS_TIMEOUT) {
  1865. if (IS_FWI2_CAPABLE(ha))
  1866. break;
  1867. else if ((le16_to_cpu(sts->status_flags) &
  1868. SF_LOGOUT_SENT) == 0)
  1869. break;
  1870. }
  1871. ql_dbg(ql_dbg_io, fcport->vha, 0x3021,
  1872. "Port down status: port-state=0x%x.\n",
  1873. atomic_read(&fcport->state));
  1874. if (atomic_read(&fcport->state) == FCS_ONLINE)
  1875. qla2x00_mark_device_lost(fcport->vha, fcport, 1, 1);
  1876. break;
  1877. case CS_ABORTED:
  1878. res = DID_RESET << 16;
  1879. break;
  1880. case CS_DIF_ERROR:
  1881. logit = qla2x00_handle_dif_error(sp, sts24);
  1882. break;
  1883. default:
  1884. res = DID_ERROR << 16;
  1885. break;
  1886. }
  1887. out:
  1888. if (logit)
  1889. ql_dbg(ql_dbg_io, fcport->vha, 0x3022,
  1890. "FCP command status: 0x%x-0x%x (0x%x) "
  1891. "nexus=%ld:%d:%d portid=%02x%02x%02x oxid=0x%x "
  1892. "cdb=%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x len=0x%x "
  1893. "rsp_info=0x%x resid=0x%x fw_resid=0x%x.\n",
  1894. comp_status, scsi_status, res, vha->host_no,
  1895. cp->device->id, cp->device->lun, fcport->d_id.b.domain,
  1896. fcport->d_id.b.area, fcport->d_id.b.al_pa, ox_id,
  1897. cp->cmnd[0], cp->cmnd[1], cp->cmnd[2], cp->cmnd[3],
  1898. cp->cmnd[4], cp->cmnd[5], cp->cmnd[6], cp->cmnd[7],
  1899. cp->cmnd[8], cp->cmnd[9], scsi_bufflen(cp), rsp_info_len,
  1900. resid_len, fw_resid_len);
  1901. if (rsp->status_srb == NULL)
  1902. sp->done(ha, sp, res);
  1903. }
  1904. /**
  1905. * qla2x00_status_cont_entry() - Process a Status Continuations entry.
  1906. * @ha: SCSI driver HA context
  1907. * @pkt: Entry pointer
  1908. *
  1909. * Extended sense data.
  1910. */
  1911. static void
  1912. qla2x00_status_cont_entry(struct rsp_que *rsp, sts_cont_entry_t *pkt)
  1913. {
  1914. uint8_t sense_sz = 0;
  1915. struct qla_hw_data *ha = rsp->hw;
  1916. struct scsi_qla_host *vha = pci_get_drvdata(ha->pdev);
  1917. srb_t *sp = rsp->status_srb;
  1918. struct scsi_cmnd *cp;
  1919. uint32_t sense_len;
  1920. uint8_t *sense_ptr;
  1921. if (!sp || !GET_CMD_SENSE_LEN(sp))
  1922. return;
  1923. sense_len = GET_CMD_SENSE_LEN(sp);
  1924. sense_ptr = GET_CMD_SENSE_PTR(sp);
  1925. cp = GET_CMD_SP(sp);
  1926. if (cp == NULL) {
  1927. ql_log(ql_log_warn, vha, 0x3025,
  1928. "cmd is NULL: already returned to OS (sp=%p).\n", sp);
  1929. rsp->status_srb = NULL;
  1930. return;
  1931. }
  1932. if (sense_len > sizeof(pkt->data))
  1933. sense_sz = sizeof(pkt->data);
  1934. else
  1935. sense_sz = sense_len;
  1936. /* Move sense data. */
  1937. if (IS_FWI2_CAPABLE(ha))
  1938. host_to_fcp_swap(pkt->data, sizeof(pkt->data));
  1939. memcpy(sense_ptr, pkt->data, sense_sz);
  1940. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x302c,
  1941. sense_ptr, sense_sz);
  1942. sense_len -= sense_sz;
  1943. sense_ptr += sense_sz;
  1944. SET_CMD_SENSE_PTR(sp, sense_ptr);
  1945. SET_CMD_SENSE_LEN(sp, sense_len);
  1946. /* Place command on done queue. */
  1947. if (sense_len == 0) {
  1948. rsp->status_srb = NULL;
  1949. sp->done(ha, sp, cp->result);
  1950. }
  1951. }
  1952. /**
  1953. * qla2x00_error_entry() - Process an error entry.
  1954. * @ha: SCSI driver HA context
  1955. * @pkt: Entry pointer
  1956. */
  1957. static void
  1958. qla2x00_error_entry(scsi_qla_host_t *vha, struct rsp_que *rsp, sts_entry_t *pkt)
  1959. {
  1960. srb_t *sp;
  1961. struct qla_hw_data *ha = vha->hw;
  1962. const char func[] = "ERROR-IOCB";
  1963. uint16_t que = MSW(pkt->handle);
  1964. struct req_que *req = NULL;
  1965. int res = DID_ERROR << 16;
  1966. ql_dbg(ql_dbg_async, vha, 0x502a,
  1967. "type of error status in response: 0x%x\n", pkt->entry_status);
  1968. if (que >= ha->max_req_queues || !ha->req_q_map[que])
  1969. goto fatal;
  1970. req = ha->req_q_map[que];
  1971. if (pkt->entry_status & RF_BUSY)
  1972. res = DID_BUS_BUSY << 16;
  1973. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  1974. if (sp) {
  1975. sp->done(ha, sp, res);
  1976. return;
  1977. }
  1978. fatal:
  1979. ql_log(ql_log_warn, vha, 0x5030,
  1980. "Error entry - invalid handle/queue.\n");
  1981. if (IS_QLA82XX(ha))
  1982. set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
  1983. else
  1984. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1985. qla2xxx_wake_dpc(vha);
  1986. }
  1987. /**
  1988. * qla24xx_mbx_completion() - Process mailbox command completions.
  1989. * @ha: SCSI driver HA context
  1990. * @mb0: Mailbox0 register
  1991. */
  1992. static void
  1993. qla24xx_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0)
  1994. {
  1995. uint16_t cnt;
  1996. uint32_t mboxes;
  1997. uint16_t __iomem *wptr;
  1998. struct qla_hw_data *ha = vha->hw;
  1999. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  2000. /* Read all mbox registers? */
  2001. mboxes = (1 << ha->mbx_count) - 1;
  2002. if (!ha->mcp)
  2003. ql_dbg(ql_dbg_async, vha, 0x504e, "MBX pointer ERRROR.\n");
  2004. else
  2005. mboxes = ha->mcp->in_mb;
  2006. /* Load return mailbox registers. */
  2007. ha->flags.mbox_int = 1;
  2008. ha->mailbox_out[0] = mb0;
  2009. mboxes >>= 1;
  2010. wptr = (uint16_t __iomem *)&reg->mailbox1;
  2011. for (cnt = 1; cnt < ha->mbx_count; cnt++) {
  2012. if (mboxes & BIT_0)
  2013. ha->mailbox_out[cnt] = RD_REG_WORD(wptr);
  2014. mboxes >>= 1;
  2015. wptr++;
  2016. }
  2017. }
  2018. /**
  2019. * qla24xx_process_response_queue() - Process response queue entries.
  2020. * @ha: SCSI driver HA context
  2021. */
  2022. void qla24xx_process_response_queue(struct scsi_qla_host *vha,
  2023. struct rsp_que *rsp)
  2024. {
  2025. struct sts_entry_24xx *pkt;
  2026. struct qla_hw_data *ha = vha->hw;
  2027. if (!vha->flags.online)
  2028. return;
  2029. while (rsp->ring_ptr->signature != RESPONSE_PROCESSED) {
  2030. pkt = (struct sts_entry_24xx *)rsp->ring_ptr;
  2031. rsp->ring_index++;
  2032. if (rsp->ring_index == rsp->length) {
  2033. rsp->ring_index = 0;
  2034. rsp->ring_ptr = rsp->ring;
  2035. } else {
  2036. rsp->ring_ptr++;
  2037. }
  2038. if (pkt->entry_status != 0) {
  2039. qla2x00_error_entry(vha, rsp, (sts_entry_t *) pkt);
  2040. (void)qlt_24xx_process_response_error(vha, pkt);
  2041. ((response_t *)pkt)->signature = RESPONSE_PROCESSED;
  2042. wmb();
  2043. continue;
  2044. }
  2045. switch (pkt->entry_type) {
  2046. case STATUS_TYPE:
  2047. qla2x00_status_entry(vha, rsp, pkt);
  2048. break;
  2049. case STATUS_CONT_TYPE:
  2050. qla2x00_status_cont_entry(rsp, (sts_cont_entry_t *)pkt);
  2051. break;
  2052. case VP_RPT_ID_IOCB_TYPE:
  2053. qla24xx_report_id_acquisition(vha,
  2054. (struct vp_rpt_id_entry_24xx *)pkt);
  2055. break;
  2056. case LOGINOUT_PORT_IOCB_TYPE:
  2057. qla24xx_logio_entry(vha, rsp->req,
  2058. (struct logio_entry_24xx *)pkt);
  2059. break;
  2060. case TSK_MGMT_IOCB_TYPE:
  2061. qla24xx_tm_iocb_entry(vha, rsp->req,
  2062. (struct tsk_mgmt_entry *)pkt);
  2063. break;
  2064. case CT_IOCB_TYPE:
  2065. qla24xx_els_ct_entry(vha, rsp->req, pkt, CT_IOCB_TYPE);
  2066. break;
  2067. case ELS_IOCB_TYPE:
  2068. qla24xx_els_ct_entry(vha, rsp->req, pkt, ELS_IOCB_TYPE);
  2069. break;
  2070. case ABTS_RECV_24XX:
  2071. /* ensure that the ATIO queue is empty */
  2072. qlt_24xx_process_atio_queue(vha);
  2073. case ABTS_RESP_24XX:
  2074. case CTIO_TYPE7:
  2075. case NOTIFY_ACK_TYPE:
  2076. qlt_response_pkt_all_vps(vha, (response_t *)pkt);
  2077. break;
  2078. case MARKER_TYPE:
  2079. /* Do nothing in this case, this check is to prevent it
  2080. * from falling into default case
  2081. */
  2082. break;
  2083. default:
  2084. /* Type Not Supported. */
  2085. ql_dbg(ql_dbg_async, vha, 0x5042,
  2086. "Received unknown response pkt type %x "
  2087. "entry status=%x.\n",
  2088. pkt->entry_type, pkt->entry_status);
  2089. break;
  2090. }
  2091. ((response_t *)pkt)->signature = RESPONSE_PROCESSED;
  2092. wmb();
  2093. }
  2094. /* Adjust ring index */
  2095. if (IS_QLA82XX(ha)) {
  2096. struct device_reg_82xx __iomem *reg = &ha->iobase->isp82;
  2097. WRT_REG_DWORD(&reg->rsp_q_out[0], rsp->ring_index);
  2098. } else
  2099. WRT_REG_DWORD(rsp->rsp_q_out, rsp->ring_index);
  2100. }
  2101. static void
  2102. qla2xxx_check_risc_status(scsi_qla_host_t *vha)
  2103. {
  2104. int rval;
  2105. uint32_t cnt;
  2106. struct qla_hw_data *ha = vha->hw;
  2107. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  2108. if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha))
  2109. return;
  2110. rval = QLA_SUCCESS;
  2111. WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
  2112. RD_REG_DWORD(&reg->iobase_addr);
  2113. WRT_REG_DWORD(&reg->iobase_window, 0x0001);
  2114. for (cnt = 10000; (RD_REG_DWORD(&reg->iobase_window) & BIT_0) == 0 &&
  2115. rval == QLA_SUCCESS; cnt--) {
  2116. if (cnt) {
  2117. WRT_REG_DWORD(&reg->iobase_window, 0x0001);
  2118. udelay(10);
  2119. } else
  2120. rval = QLA_FUNCTION_TIMEOUT;
  2121. }
  2122. if (rval == QLA_SUCCESS)
  2123. goto next_test;
  2124. WRT_REG_DWORD(&reg->iobase_window, 0x0003);
  2125. for (cnt = 100; (RD_REG_DWORD(&reg->iobase_window) & BIT_0) == 0 &&
  2126. rval == QLA_SUCCESS; cnt--) {
  2127. if (cnt) {
  2128. WRT_REG_DWORD(&reg->iobase_window, 0x0003);
  2129. udelay(10);
  2130. } else
  2131. rval = QLA_FUNCTION_TIMEOUT;
  2132. }
  2133. if (rval != QLA_SUCCESS)
  2134. goto done;
  2135. next_test:
  2136. if (RD_REG_DWORD(&reg->iobase_c8) & BIT_3)
  2137. ql_log(ql_log_info, vha, 0x504c,
  2138. "Additional code -- 0x55AA.\n");
  2139. done:
  2140. WRT_REG_DWORD(&reg->iobase_window, 0x0000);
  2141. RD_REG_DWORD(&reg->iobase_window);
  2142. }
  2143. /**
  2144. * qla24xx_intr_handler() - Process interrupts for the ISP23xx and ISP24xx.
  2145. * @irq:
  2146. * @dev_id: SCSI driver HA context
  2147. *
  2148. * Called by system whenever the host adapter generates an interrupt.
  2149. *
  2150. * Returns handled flag.
  2151. */
  2152. irqreturn_t
  2153. qla24xx_intr_handler(int irq, void *dev_id)
  2154. {
  2155. scsi_qla_host_t *vha;
  2156. struct qla_hw_data *ha;
  2157. struct device_reg_24xx __iomem *reg;
  2158. int status;
  2159. unsigned long iter;
  2160. uint32_t stat;
  2161. uint32_t hccr;
  2162. uint16_t mb[8];
  2163. struct rsp_que *rsp;
  2164. unsigned long flags;
  2165. rsp = (struct rsp_que *) dev_id;
  2166. if (!rsp) {
  2167. ql_log(ql_log_info, NULL, 0x5059,
  2168. "%s: NULL response queue pointer.\n", __func__);
  2169. return IRQ_NONE;
  2170. }
  2171. ha = rsp->hw;
  2172. reg = &ha->iobase->isp24;
  2173. status = 0;
  2174. if (unlikely(pci_channel_offline(ha->pdev)))
  2175. return IRQ_HANDLED;
  2176. spin_lock_irqsave(&ha->hardware_lock, flags);
  2177. vha = pci_get_drvdata(ha->pdev);
  2178. for (iter = 50; iter--; ) {
  2179. stat = RD_REG_DWORD(&reg->host_status);
  2180. if (stat & HSRX_RISC_PAUSED) {
  2181. if (unlikely(pci_channel_offline(ha->pdev)))
  2182. break;
  2183. hccr = RD_REG_DWORD(&reg->hccr);
  2184. ql_log(ql_log_warn, vha, 0x504b,
  2185. "RISC paused -- HCCR=%x, Dumping firmware.\n",
  2186. hccr);
  2187. qla2xxx_check_risc_status(vha);
  2188. ha->isp_ops->fw_dump(vha, 1);
  2189. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2190. break;
  2191. } else if ((stat & HSRX_RISC_INT) == 0)
  2192. break;
  2193. switch (stat & 0xff) {
  2194. case 0x1:
  2195. case 0x2:
  2196. case 0x10:
  2197. case 0x11:
  2198. qla24xx_mbx_completion(vha, MSW(stat));
  2199. status |= MBX_INTERRUPT;
  2200. break;
  2201. case 0x12:
  2202. mb[0] = MSW(stat);
  2203. mb[1] = RD_REG_WORD(&reg->mailbox1);
  2204. mb[2] = RD_REG_WORD(&reg->mailbox2);
  2205. mb[3] = RD_REG_WORD(&reg->mailbox3);
  2206. qla2x00_async_event(vha, rsp, mb);
  2207. break;
  2208. case 0x13:
  2209. case 0x14:
  2210. qla24xx_process_response_queue(vha, rsp);
  2211. break;
  2212. case 0x1C: /* ATIO queue updated */
  2213. qlt_24xx_process_atio_queue(vha);
  2214. break;
  2215. case 0x1D: /* ATIO and response queues updated */
  2216. qlt_24xx_process_atio_queue(vha);
  2217. qla24xx_process_response_queue(vha, rsp);
  2218. break;
  2219. default:
  2220. ql_dbg(ql_dbg_async, vha, 0x504f,
  2221. "Unrecognized interrupt type (%d).\n", stat * 0xff);
  2222. break;
  2223. }
  2224. WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
  2225. RD_REG_DWORD_RELAXED(&reg->hccr);
  2226. }
  2227. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2228. if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) &&
  2229. (status & MBX_INTERRUPT) && ha->flags.mbox_int) {
  2230. set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  2231. complete(&ha->mbx_intr_comp);
  2232. }
  2233. return IRQ_HANDLED;
  2234. }
  2235. static irqreturn_t
  2236. qla24xx_msix_rsp_q(int irq, void *dev_id)
  2237. {
  2238. struct qla_hw_data *ha;
  2239. struct rsp_que *rsp;
  2240. struct device_reg_24xx __iomem *reg;
  2241. struct scsi_qla_host *vha;
  2242. unsigned long flags;
  2243. rsp = (struct rsp_que *) dev_id;
  2244. if (!rsp) {
  2245. ql_log(ql_log_info, NULL, 0x505a,
  2246. "%s: NULL response queue pointer.\n", __func__);
  2247. return IRQ_NONE;
  2248. }
  2249. ha = rsp->hw;
  2250. reg = &ha->iobase->isp24;
  2251. spin_lock_irqsave(&ha->hardware_lock, flags);
  2252. vha = pci_get_drvdata(ha->pdev);
  2253. qla24xx_process_response_queue(vha, rsp);
  2254. if (!ha->flags.disable_msix_handshake) {
  2255. WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
  2256. RD_REG_DWORD_RELAXED(&reg->hccr);
  2257. }
  2258. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2259. return IRQ_HANDLED;
  2260. }
  2261. static irqreturn_t
  2262. qla25xx_msix_rsp_q(int irq, void *dev_id)
  2263. {
  2264. struct qla_hw_data *ha;
  2265. struct rsp_que *rsp;
  2266. struct device_reg_24xx __iomem *reg;
  2267. unsigned long flags;
  2268. rsp = (struct rsp_que *) dev_id;
  2269. if (!rsp) {
  2270. ql_log(ql_log_info, NULL, 0x505b,
  2271. "%s: NULL response queue pointer.\n", __func__);
  2272. return IRQ_NONE;
  2273. }
  2274. ha = rsp->hw;
  2275. /* Clear the interrupt, if enabled, for this response queue */
  2276. if (!ha->flags.disable_msix_handshake) {
  2277. reg = &ha->iobase->isp24;
  2278. spin_lock_irqsave(&ha->hardware_lock, flags);
  2279. WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
  2280. RD_REG_DWORD_RELAXED(&reg->hccr);
  2281. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2282. }
  2283. queue_work_on((int) (rsp->id - 1), ha->wq, &rsp->q_work);
  2284. return IRQ_HANDLED;
  2285. }
  2286. static irqreturn_t
  2287. qla24xx_msix_default(int irq, void *dev_id)
  2288. {
  2289. scsi_qla_host_t *vha;
  2290. struct qla_hw_data *ha;
  2291. struct rsp_que *rsp;
  2292. struct device_reg_24xx __iomem *reg;
  2293. int status;
  2294. uint32_t stat;
  2295. uint32_t hccr;
  2296. uint16_t mb[8];
  2297. unsigned long flags;
  2298. rsp = (struct rsp_que *) dev_id;
  2299. if (!rsp) {
  2300. ql_log(ql_log_info, NULL, 0x505c,
  2301. "%s: NULL response queue pointer.\n", __func__);
  2302. return IRQ_NONE;
  2303. }
  2304. ha = rsp->hw;
  2305. reg = &ha->iobase->isp24;
  2306. status = 0;
  2307. spin_lock_irqsave(&ha->hardware_lock, flags);
  2308. vha = pci_get_drvdata(ha->pdev);
  2309. do {
  2310. stat = RD_REG_DWORD(&reg->host_status);
  2311. if (stat & HSRX_RISC_PAUSED) {
  2312. if (unlikely(pci_channel_offline(ha->pdev)))
  2313. break;
  2314. hccr = RD_REG_DWORD(&reg->hccr);
  2315. ql_log(ql_log_info, vha, 0x5050,
  2316. "RISC paused -- HCCR=%x, Dumping firmware.\n",
  2317. hccr);
  2318. qla2xxx_check_risc_status(vha);
  2319. ha->isp_ops->fw_dump(vha, 1);
  2320. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2321. break;
  2322. } else if ((stat & HSRX_RISC_INT) == 0)
  2323. break;
  2324. switch (stat & 0xff) {
  2325. case 0x1:
  2326. case 0x2:
  2327. case 0x10:
  2328. case 0x11:
  2329. qla24xx_mbx_completion(vha, MSW(stat));
  2330. status |= MBX_INTERRUPT;
  2331. break;
  2332. case 0x12:
  2333. mb[0] = MSW(stat);
  2334. mb[1] = RD_REG_WORD(&reg->mailbox1);
  2335. mb[2] = RD_REG_WORD(&reg->mailbox2);
  2336. mb[3] = RD_REG_WORD(&reg->mailbox3);
  2337. qla2x00_async_event(vha, rsp, mb);
  2338. break;
  2339. case 0x13:
  2340. case 0x14:
  2341. qla24xx_process_response_queue(vha, rsp);
  2342. break;
  2343. case 0x1C: /* ATIO queue updated */
  2344. qlt_24xx_process_atio_queue(vha);
  2345. break;
  2346. case 0x1D: /* ATIO and response queues updated */
  2347. qlt_24xx_process_atio_queue(vha);
  2348. qla24xx_process_response_queue(vha, rsp);
  2349. break;
  2350. default:
  2351. ql_dbg(ql_dbg_async, vha, 0x5051,
  2352. "Unrecognized interrupt type (%d).\n", stat & 0xff);
  2353. break;
  2354. }
  2355. WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
  2356. } while (0);
  2357. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2358. if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) &&
  2359. (status & MBX_INTERRUPT) && ha->flags.mbox_int) {
  2360. set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  2361. complete(&ha->mbx_intr_comp);
  2362. }
  2363. return IRQ_HANDLED;
  2364. }
  2365. /* Interrupt handling helpers. */
  2366. struct qla_init_msix_entry {
  2367. const char *name;
  2368. irq_handler_t handler;
  2369. };
  2370. static struct qla_init_msix_entry msix_entries[3] = {
  2371. { "qla2xxx (default)", qla24xx_msix_default },
  2372. { "qla2xxx (rsp_q)", qla24xx_msix_rsp_q },
  2373. { "qla2xxx (multiq)", qla25xx_msix_rsp_q },
  2374. };
  2375. static struct qla_init_msix_entry qla82xx_msix_entries[2] = {
  2376. { "qla2xxx (default)", qla82xx_msix_default },
  2377. { "qla2xxx (rsp_q)", qla82xx_msix_rsp_q },
  2378. };
  2379. static void
  2380. qla24xx_disable_msix(struct qla_hw_data *ha)
  2381. {
  2382. int i;
  2383. struct qla_msix_entry *qentry;
  2384. scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
  2385. for (i = 0; i < ha->msix_count; i++) {
  2386. qentry = &ha->msix_entries[i];
  2387. if (qentry->have_irq)
  2388. free_irq(qentry->vector, qentry->rsp);
  2389. }
  2390. pci_disable_msix(ha->pdev);
  2391. kfree(ha->msix_entries);
  2392. ha->msix_entries = NULL;
  2393. ha->flags.msix_enabled = 0;
  2394. ql_dbg(ql_dbg_init, vha, 0x0042,
  2395. "Disabled the MSI.\n");
  2396. }
  2397. static int
  2398. qla24xx_enable_msix(struct qla_hw_data *ha, struct rsp_que *rsp)
  2399. {
  2400. #define MIN_MSIX_COUNT 2
  2401. int i, ret;
  2402. struct msix_entry *entries;
  2403. struct qla_msix_entry *qentry;
  2404. scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
  2405. entries = kzalloc(sizeof(struct msix_entry) * ha->msix_count,
  2406. GFP_KERNEL);
  2407. if (!entries) {
  2408. ql_log(ql_log_warn, vha, 0x00bc,
  2409. "Failed to allocate memory for msix_entry.\n");
  2410. return -ENOMEM;
  2411. }
  2412. for (i = 0; i < ha->msix_count; i++)
  2413. entries[i].entry = i;
  2414. ret = pci_enable_msix(ha->pdev, entries, ha->msix_count);
  2415. if (ret) {
  2416. if (ret < MIN_MSIX_COUNT)
  2417. goto msix_failed;
  2418. ql_log(ql_log_warn, vha, 0x00c6,
  2419. "MSI-X: Failed to enable support "
  2420. "-- %d/%d\n Retry with %d vectors.\n",
  2421. ha->msix_count, ret, ret);
  2422. ha->msix_count = ret;
  2423. ret = pci_enable_msix(ha->pdev, entries, ha->msix_count);
  2424. if (ret) {
  2425. msix_failed:
  2426. ql_log(ql_log_fatal, vha, 0x00c7,
  2427. "MSI-X: Failed to enable support, "
  2428. "giving up -- %d/%d.\n",
  2429. ha->msix_count, ret);
  2430. goto msix_out;
  2431. }
  2432. ha->max_rsp_queues = ha->msix_count - 1;
  2433. }
  2434. ha->msix_entries = kzalloc(sizeof(struct qla_msix_entry) *
  2435. ha->msix_count, GFP_KERNEL);
  2436. if (!ha->msix_entries) {
  2437. ql_log(ql_log_fatal, vha, 0x00c8,
  2438. "Failed to allocate memory for ha->msix_entries.\n");
  2439. ret = -ENOMEM;
  2440. goto msix_out;
  2441. }
  2442. ha->flags.msix_enabled = 1;
  2443. for (i = 0; i < ha->msix_count; i++) {
  2444. qentry = &ha->msix_entries[i];
  2445. qentry->vector = entries[i].vector;
  2446. qentry->entry = entries[i].entry;
  2447. qentry->have_irq = 0;
  2448. qentry->rsp = NULL;
  2449. }
  2450. /* Enable MSI-X vectors for the base queue */
  2451. for (i = 0; i < 2; i++) {
  2452. qentry = &ha->msix_entries[i];
  2453. if (IS_QLA82XX(ha)) {
  2454. ret = request_irq(qentry->vector,
  2455. qla82xx_msix_entries[i].handler,
  2456. 0, qla82xx_msix_entries[i].name, rsp);
  2457. } else {
  2458. ret = request_irq(qentry->vector,
  2459. msix_entries[i].handler,
  2460. 0, msix_entries[i].name, rsp);
  2461. }
  2462. if (ret) {
  2463. ql_log(ql_log_fatal, vha, 0x00cb,
  2464. "MSI-X: unable to register handler -- %x/%d.\n",
  2465. qentry->vector, ret);
  2466. qla24xx_disable_msix(ha);
  2467. ha->mqenable = 0;
  2468. goto msix_out;
  2469. }
  2470. qentry->have_irq = 1;
  2471. qentry->rsp = rsp;
  2472. rsp->msix = qentry;
  2473. }
  2474. /* Enable MSI-X vector for response queue update for queue 0 */
  2475. if (IS_QLA83XX(ha)) {
  2476. if (ha->msixbase && ha->mqiobase &&
  2477. (ha->max_rsp_queues > 1 || ha->max_req_queues > 1))
  2478. ha->mqenable = 1;
  2479. } else
  2480. if (ha->mqiobase
  2481. && (ha->max_rsp_queues > 1 || ha->max_req_queues > 1))
  2482. ha->mqenable = 1;
  2483. ql_dbg(ql_dbg_multiq, vha, 0xc005,
  2484. "mqiobase=%p, max_rsp_queues=%d, max_req_queues=%d.\n",
  2485. ha->mqiobase, ha->max_rsp_queues, ha->max_req_queues);
  2486. ql_dbg(ql_dbg_init, vha, 0x0055,
  2487. "mqiobase=%p, max_rsp_queues=%d, max_req_queues=%d.\n",
  2488. ha->mqiobase, ha->max_rsp_queues, ha->max_req_queues);
  2489. msix_out:
  2490. kfree(entries);
  2491. return ret;
  2492. }
  2493. int
  2494. qla2x00_request_irqs(struct qla_hw_data *ha, struct rsp_que *rsp)
  2495. {
  2496. int ret;
  2497. device_reg_t __iomem *reg = ha->iobase;
  2498. scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
  2499. /* If possible, enable MSI-X. */
  2500. if (!IS_QLA2432(ha) && !IS_QLA2532(ha) && !IS_QLA8432(ha) &&
  2501. !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha))
  2502. goto skip_msi;
  2503. if (ha->pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
  2504. (ha->pdev->subsystem_device == 0x7040 ||
  2505. ha->pdev->subsystem_device == 0x7041 ||
  2506. ha->pdev->subsystem_device == 0x1705)) {
  2507. ql_log(ql_log_warn, vha, 0x0034,
  2508. "MSI-X: Unsupported ISP 2432 SSVID/SSDID (0x%X,0x%X).\n",
  2509. ha->pdev->subsystem_vendor,
  2510. ha->pdev->subsystem_device);
  2511. goto skip_msi;
  2512. }
  2513. if (IS_QLA2432(ha) && (ha->pdev->revision < QLA_MSIX_CHIP_REV_24XX)) {
  2514. ql_log(ql_log_warn, vha, 0x0035,
  2515. "MSI-X; Unsupported ISP2432 (0x%X, 0x%X).\n",
  2516. ha->pdev->revision, QLA_MSIX_CHIP_REV_24XX);
  2517. goto skip_msix;
  2518. }
  2519. ret = qla24xx_enable_msix(ha, rsp);
  2520. if (!ret) {
  2521. ql_dbg(ql_dbg_init, vha, 0x0036,
  2522. "MSI-X: Enabled (0x%X, 0x%X).\n",
  2523. ha->chip_revision, ha->fw_attributes);
  2524. goto clear_risc_ints;
  2525. }
  2526. ql_log(ql_log_info, vha, 0x0037,
  2527. "MSI-X Falling back-to MSI mode -%d.\n", ret);
  2528. skip_msix:
  2529. if (!IS_QLA24XX(ha) && !IS_QLA2532(ha) && !IS_QLA8432(ha) &&
  2530. !IS_QLA8001(ha))
  2531. goto skip_msi;
  2532. ret = pci_enable_msi(ha->pdev);
  2533. if (!ret) {
  2534. ql_dbg(ql_dbg_init, vha, 0x0038,
  2535. "MSI: Enabled.\n");
  2536. ha->flags.msi_enabled = 1;
  2537. } else
  2538. ql_log(ql_log_warn, vha, 0x0039,
  2539. "MSI-X; Falling back-to INTa mode -- %d.\n", ret);
  2540. skip_msi:
  2541. ret = request_irq(ha->pdev->irq, ha->isp_ops->intr_handler,
  2542. ha->flags.msi_enabled ? 0 : IRQF_SHARED,
  2543. QLA2XXX_DRIVER_NAME, rsp);
  2544. if (ret) {
  2545. ql_log(ql_log_warn, vha, 0x003a,
  2546. "Failed to reserve interrupt %d already in use.\n",
  2547. ha->pdev->irq);
  2548. goto fail;
  2549. }
  2550. clear_risc_ints:
  2551. /*
  2552. * FIXME: Noted that 8014s were being dropped during NK testing.
  2553. * Timing deltas during MSI-X/INTa transitions?
  2554. */
  2555. if (IS_QLA81XX(ha) || IS_QLA82XX(ha) || IS_QLA83XX(ha))
  2556. goto fail;
  2557. spin_lock_irq(&ha->hardware_lock);
  2558. if (IS_FWI2_CAPABLE(ha)) {
  2559. WRT_REG_DWORD(&reg->isp24.hccr, HCCRX_CLR_HOST_INT);
  2560. WRT_REG_DWORD(&reg->isp24.hccr, HCCRX_CLR_RISC_INT);
  2561. } else {
  2562. WRT_REG_WORD(&reg->isp.semaphore, 0);
  2563. WRT_REG_WORD(&reg->isp.hccr, HCCR_CLR_RISC_INT);
  2564. WRT_REG_WORD(&reg->isp.hccr, HCCR_CLR_HOST_INT);
  2565. }
  2566. spin_unlock_irq(&ha->hardware_lock);
  2567. fail:
  2568. return ret;
  2569. }
  2570. void
  2571. qla2x00_free_irqs(scsi_qla_host_t *vha)
  2572. {
  2573. struct qla_hw_data *ha = vha->hw;
  2574. struct rsp_que *rsp;
  2575. /*
  2576. * We need to check that ha->rsp_q_map is valid in case we are called
  2577. * from a probe failure context.
  2578. */
  2579. if (!ha->rsp_q_map || !ha->rsp_q_map[0])
  2580. return;
  2581. rsp = ha->rsp_q_map[0];
  2582. if (ha->flags.msix_enabled)
  2583. qla24xx_disable_msix(ha);
  2584. else if (ha->flags.msi_enabled) {
  2585. free_irq(ha->pdev->irq, rsp);
  2586. pci_disable_msi(ha->pdev);
  2587. } else
  2588. free_irq(ha->pdev->irq, rsp);
  2589. }
  2590. int qla25xx_request_irq(struct rsp_que *rsp)
  2591. {
  2592. struct qla_hw_data *ha = rsp->hw;
  2593. struct qla_init_msix_entry *intr = &msix_entries[2];
  2594. struct qla_msix_entry *msix = rsp->msix;
  2595. scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
  2596. int ret;
  2597. ret = request_irq(msix->vector, intr->handler, 0, intr->name, rsp);
  2598. if (ret) {
  2599. ql_log(ql_log_fatal, vha, 0x00e6,
  2600. "MSI-X: Unable to register handler -- %x/%d.\n",
  2601. msix->vector, ret);
  2602. return ret;
  2603. }
  2604. msix->have_irq = 1;
  2605. msix->rsp = rsp;
  2606. return ret;
  2607. }