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@@ -121,21 +121,16 @@ static void omap_dm_timer_wait_for_reset(struct omap_dm_timer *timer)
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static void omap_dm_timer_reset(struct omap_dm_timer *timer)
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{
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- omap_dm_timer_enable(timer);
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if (timer->pdev->id != 1) {
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omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
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omap_dm_timer_wait_for_reset(timer);
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}
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__omap_dm_timer_reset(timer, 0, 0);
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- __omap_dm_timer_enable_posted(timer);
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- omap_dm_timer_disable(timer);
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}
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int omap_dm_timer_prepare(struct omap_dm_timer *timer)
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{
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- int ret;
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-
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/*
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* FIXME: OMAP1 devices do not use the clock framework for dmtimers so
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* do not call clk_get() for these devices.
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@@ -149,13 +144,15 @@ int omap_dm_timer_prepare(struct omap_dm_timer *timer)
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}
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}
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+ omap_dm_timer_enable(timer);
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+
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if (timer->capability & OMAP_TIMER_NEEDS_RESET)
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omap_dm_timer_reset(timer);
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- ret = omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ);
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+ __omap_dm_timer_enable_posted(timer);
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+ omap_dm_timer_disable(timer);
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- timer->posted = 1;
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- return ret;
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+ return omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ);
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}
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static inline u32 omap_dm_timer_reserved_systimer(int id)
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