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@@ -756,18 +756,19 @@ static void pump_transfers(unsigned long data)
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if (!full_duplex && drv_data->cur_chip->enable_dma
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&& drv_data->len > 6) {
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+ unsigned long dma_start_addr;
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+
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disable_dma(drv_data->dma_channel);
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clear_dma_irqstat(drv_data->dma_channel);
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bfin_spi_disable(drv_data);
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/* config dma channel */
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dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n");
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+ set_dma_x_count(drv_data->dma_channel, drv_data->len);
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if (width == CFG_SPI_WORDSIZE16) {
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- set_dma_x_count(drv_data->dma_channel, drv_data->len);
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set_dma_x_modify(drv_data->dma_channel, 2);
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dma_width = WDSIZE_16;
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} else {
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- set_dma_x_count(drv_data->dma_channel, drv_data->len);
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set_dma_x_modify(drv_data->dma_channel, 1);
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dma_width = WDSIZE_8;
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}
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@@ -802,6 +803,7 @@ static void pump_transfers(unsigned long data)
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}
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/* In dma mode, rx or tx must be NULL in one transfer */
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+ dma_config = (RESTART | dma_width | DI_EN);
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if (drv_data->rx != NULL) {
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/* set transfer mode, and enable SPI */
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dev_dbg(&drv_data->pdev->dev, "doing DMA in.\n");
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@@ -815,19 +817,9 @@ static void pump_transfers(unsigned long data)
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/* clear tx reg soformer data is not shifted out */
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write_TDBR(drv_data, 0xFFFF);
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- set_dma_x_count(drv_data->dma_channel, drv_data->len);
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-
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- /* start dma */
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- dma_enable_irq(drv_data->dma_channel);
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- dma_config = (WNR | RESTART | dma_width | DI_EN);
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- set_dma_config(drv_data->dma_channel, dma_config);
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- set_dma_start_addr(drv_data->dma_channel,
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- (unsigned long)drv_data->rx);
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- enable_dma(drv_data->dma_channel);
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-
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- /* start SPI transfer */
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- write_CTRL(drv_data,
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- (cr | CFG_SPI_DMAREAD | BIT_CTL_ENABLE));
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+ dma_config |= WNR;
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+ dma_start_addr = (unsigned long)drv_data->rx;
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+ cr |= CFG_SPI_DMAREAD;
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} else if (drv_data->tx != NULL) {
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dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n");
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@@ -838,18 +830,21 @@ static void pump_transfers(unsigned long data)
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(unsigned long) (drv_data->tx +
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drv_data->len_in_bytes));
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- /* start dma */
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- dma_enable_irq(drv_data->dma_channel);
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- dma_config = (RESTART | dma_width | DI_EN);
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- set_dma_config(drv_data->dma_channel, dma_config);
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- set_dma_start_addr(drv_data->dma_channel,
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- (unsigned long)drv_data->tx);
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- enable_dma(drv_data->dma_channel);
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+ dma_start_addr = (unsigned long)drv_data->tx;
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+ cr |= CFG_SPI_DMAWRITE;
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+
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+ } else
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+ BUG();
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+
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+ /* start dma */
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+ dma_enable_irq(drv_data->dma_channel);
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+ set_dma_config(drv_data->dma_channel, dma_config);
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+ set_dma_start_addr(drv_data->dma_channel, dma_start_addr);
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+ enable_dma(drv_data->dma_channel);
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+
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+ /* start SPI transfer */
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+ write_CTRL(drv_data, (cr | BIT_CTL_ENABLE));
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- /* start SPI transfer */
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- write_CTRL(drv_data,
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- (cr | CFG_SPI_DMAWRITE | BIT_CTL_ENABLE));
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- }
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} else {
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/* IO mode write then read */
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dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n");
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